2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
55 lines
2.1 KiB
Text
Executable file
55 lines
2.1 KiB
Text
Executable file
xaxiethernet_example_readme.txt
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-------------------------------
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The examples in this directory are provided to give the user some idea of
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how the Axi Ethernet and its driver are intended to be used.
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SYSTEM REQUIREMENTS
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The system containing the Axi Ethernet should have the following capabilities:
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- An interrupt controller
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- An external memory controller with at least 200KB of RAM available
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- A UART to display messages
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- The reset line of the device connected to the AxiEthernet AXI4-Stream
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interface (AXIDMA or AXIFIFO) must be connected to the reset line of AxiEthernet.
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(By default for BSB generated systems this is the case.)
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FILES
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1. xaxiethernet_example.h - Top level include for all examples.
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2. xaxiethernet_example_util.c - Provide various utilities for debugging, and
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ethernet frame construction.
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3. xaxiethernet_example_polled.c - Examples using the L1 API found in xaxiethernet.h
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in polled mode. HW must be setup for FIFO direct mode.
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4. xaxiethernet_example_intr_fifo.c - Examples using the L1 API found in
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xaxiethernet.h in interrupt driven FIFO direct mode. HW must be setup for
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FIFO direct mode.
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5. xaxiethernet_example_intr_sgdma.c - Examples using the L1 API found in
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xaxiethernet.h in interrupt driven scatter-gather DMA mode. HW must be setup
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for SGDMA mode. HW must be setup for checksum offloading for that
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specific example to properly execute.
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INCLUDING EXAMPLES IN EDK
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Each example is independent from the others except for common code found in
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xaxiethernet_example_util.c. When including source code files in an EDK SW
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application, select xaxiethernet_example_util.c along with one other example
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source code file.
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IMPORTANT NOTES
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* Included HW features are critical as to which examples will run properly.
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* The device connected to the AXI4-Stream interface (AXIFIFO or AXIDMA)
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of the AxiEthernet must be initialized before AxiEthernet initialization.
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Since the reset line of AXIFIFO or AXIDMA is connected to the reset line
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of AxiEthernet, AXIDMA/AXIFIFO initialization would reset AxiEthernet.
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AxiEthernet hardware initialization routines in the AxiEthernet driver do
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not reset the AxiEthernet hardware.
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