306 lines
14 KiB
C
306 lines
14 KiB
C
/*******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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*******************************************************************************/
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/******************************************************************************/
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/**
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*
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* @file xdp.h
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*
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* The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the
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* Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the
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* DisplayPort 1.2a specification.
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*
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* The Xilinx DisplayPort soft IP supports the following features:
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* - 1, 2, or 4 lanes.
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* - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
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* - 1, 2, or 4 pixel-wide video interfaces.
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* - RGB and YCbCr color space.
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* - Up to 16 bits per component.
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* - Up to 4Kx2K monitor resolution.
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* - Auto lane rate and width negotiation.
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* - I2C over a 1Mb/s AUX channel.
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* - Secondary channel audio support (2 channels).
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* - 4 independent video multi-streams.
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*
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* The Xilinx DisplayPort soft IP does not support the following features:
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* - The automated test feature.
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* - Audio (3-8 channel).
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* - FAUX.
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* - Bridging function.
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* - MST audio.
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* - eDP optional features.
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* - iDP.
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* - GTC.
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*
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* <b>DisplayPort overview</b>
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*
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* A DisplayPort link consists of:
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* - A unidirectional main link which is used to transport isochronous data
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* streams such as video and audio. The main link may use 1, 2, or 4
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* lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
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* needs to be trained prior to sending streams.
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* - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
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* link training, link management, and device control.
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* - A hot-plug-detect (HPD) signal line is used to determine whether a
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* DisplayPort connection exists between the DisplayPort TX connector and
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* an RX device. It is serves as an interrupt request by the RX device.
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*
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* <b>Driver description</b>
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*
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* The device driver enables higher-level software (e.g., an application) to
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* configure and control a DisplayPort TX soft IP, communicate and control an
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* RX device/sink monitor over the AUX channel, and to initialize and transmit
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* data streams over the main link.
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*
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* This driver implements link layer functionality: a Link Policy Maker (LPM)
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* and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.
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* - The LPM manages the main link and is responsible for keeping the link
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* synchronized. It will establish a link with a downstream RX device by
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* undergoing a link training sequence which consists of:
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* - Clock recovery: The clock needs to be recovered and PLLs need to be
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* locked for all lanes.
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* - Channel equalization: All lanes need to achieve channel equalization
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* and and symbol lock, as well as for interlane alignment to take place.
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* - The SPM manages transportation of an isochronous stream. That is, it will
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* initialize and maintain a video stream, establish a virtual channel to a
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* sink monitor, and transmit the stream.
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*
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* Using AUX transactions to read/write from/to the sink's DisplayPort
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* Configuration Data (DPCD) address space, the LPM obtains the link
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* capabilities, obtains link configuration and link and sink status, and
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* configures and controls the link and sink. The main link is trained this way.
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*
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* I2C-over-AUX transactions are used to obtain the sink's Extended Display
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* Identification Data (EDID) which give information on the display capabilities
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* of the monitor. The SPM may use this information to determine what available
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* screen resolutions and video timing are possible.
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*
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* <b>Device configuration</b>
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*
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* The device can be configured in various ways during the FPGA implementation
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* process. Configuration parameters are stored in the xdptx_g.c file which is
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* generated when compiling the board support package (BSP). A table is defined
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* where each entry contains configuration information for the DisplayPort
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* instances present in the system. This information includes parameters that
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* are defined in the driver's data/dptx.tcl file such as the base address of
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* the memory-mapped device and the maximum number of lanes, maximum link rate,
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* and video interface that the DisplayPort instance supports, among others.
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*
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* <b>Interrupt processing</b>
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*
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* DisplayPort interrupts occur on the HPD signal line when the DisplayPort
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* cable is connected/disconnected or when the RX device sends a pulse. The user
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* hardware design must contain an interrupt controller which the DisplayPort
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* TX instance's interrupt signal is connected to. The user application must
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* enable interrupts in the system and set up the interrupt controller such that
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* the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts.
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* When the XDptx_HpdInterruptHandler function is invoked, the handler will
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* identify what type of DisplayPort interrupt has occurred, and will call
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* either the HPD event handler function or the HPD pulse handler function,
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* depending on whether a an HPD event on an HPD pulse event occurred.
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*
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* The DisplayPort TX's XDPTX_INTERRUPT_STATUS register indicates the type of
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* interrupt that has occured, and the XDptx_HpdInterruptHandler will use this
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* information to decide which handler to call. An HPD event is identified if
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* bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
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* identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
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*
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* The HPD event handler may be set up by using the XDptx_SetHpdEventHandler
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* function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler
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* function.
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*
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* <b>Multi-stream transport (MST) mode</b>
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*
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* The driver handles MST mode functionality, including sideband messaging,
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* topology discovery, virtual channel payload ID table management, and
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* directing streams to different sinks.
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*
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* MST testing has been done at all possible link rate/lane count/topology/
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* resolution/color depth combinations with each setting using following values:
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* - Link rate: 1.62, 2.70, and 5.40Gbps per lane.
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* - Lane count: 1, 2, and 4 lanes.
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* - Number of sink displays: 1, 2, 3, and 4 sink displays in both a daisy-chain
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* configuration and in a configuration using a combination of a 1-to-3 hub
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* and daisy-chain. Each stream was using the same resolution.
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* - Resolutions (60Hz): 640x480, 800x600, 1024x768, 1280x800, 1280x1024,
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* 1360x768, 1400x1050, 1680x1050, 1920x1080, 1920x2160, and 3840x2160.
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* - Color depths: 18, 24, 30, 36, and 48 bits per pixel.
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*
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* <b>Audio</b>
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*
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* The driver does not handle audio. For an example as to how to configure and
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* transmit audio, examples/xdptx_audio_example.c illustrates the required
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* sequence. The user will need to configure the audio source connected to the
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* Displayport TX instance and set up the audio info frame as per user
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* requirements.
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*
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* <b>Asserts</b>
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*
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* Asserts are used within all Xilinx drivers to enforce constraints on argument
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* values. Asserts can be turned off on a system-wide basis by defining, at
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* compile time, the NDEBUG identifier. By default, asserts are turned on and
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* it is recommended that application developers leave asserts on during
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* development.
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*
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* <b>Limitations</b>
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*
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* - For MST mode to correctly display, the current version of the driver
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* requires that each of the DisplayPort TX streams be allocated without
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* skipping streams (i.e. assign stream 1, stream 2, and stream 3 - problems
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* were experienced if skipping stream 2 and assigning stream 4 instead).
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* skipping monitors in a daisy chain is OK as long as they are assigned to
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* streams in order.
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* - In MST mode, the current version of the driver does not support removal of
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* an allocated stream from the virtual channel payload ID table without
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* clearing the entire table.
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* - Some sideband messages have not been implemented in the current version of
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* the driver for MST mode. Notably, reception of a CONNECTION_STATUS_NOTIFY
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* sideband message.
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* - The driver does not handle audio. See the audio example in the driver
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* examples directory for the required sequence for enabling audio.
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*
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* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
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* required with a speed grade of -2 or -3.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* </pre>
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*
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*******************************************************************************/
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#ifndef XDP_H_
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/* Prevent circular inclusions by using protection macros. */
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#define XDP_H_
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/******************************* Include Files ********************************/
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#include "xil_types.h"
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/* xdprx.h and xdptx.h are included. They require some type definitions. */
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/****************************** Type Definitions ******************************/
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/**
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* This typedef contains configuration information for the DisplayPort TX core.
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*/
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typedef struct {
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u16 DeviceId; /**< Device instance ID. */
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u32 BaseAddr; /**< The base address of the core instance. */
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u32 SAxiClkHz; /**< The clock frequency of the core instance's
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S_AXI_ACLK port. */
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u8 MaxLaneCount; /**< The maximum lane count supported by this
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core instance. */
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u8 MaxLinkRate; /**< The maximum link rate supported by this
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core instance. */
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u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
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core instance*/
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u8 QuadPixelEn; /**< Quad pixel support by this core
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instance. */
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u8 DualPixelEn; /**< Dual pixel support by this core
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instance. */
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u8 YCrCbEn; /**< YCrCb format support by this core
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instance. */
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u8 YOnlyEn; /**< YOnly format support by this core
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instance. */
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u8 PayloadDataWidth; /**< The payload data width used by this core
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instance. */
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u8 SecondaryChEn; /**< This core instance supports audio packets
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being sent by the secondary channel. */
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u8 NumAudioChs; /**< The number of audio channels supported by
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this core instance. */
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u8 MstSupport; /**< Multi-stream transport (MST) mode is
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enabled by this core instance. */
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u8 NumMstStreams; /**< The total number of MST streams supported
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by this core instance. */
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u8 DpProtocol; /**< The DisplayPort protocol version that this
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core instance is configured for.
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0 = v1.1a, 1 = v1.2. */
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u8 IsRx; /**< The type of DisplayPort core.
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0 = TX, 1 = RX. */
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} XDp_Config;
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/******************************************************************************/
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/**
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* Callback type which represents a custom timer wait handler. This is only
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* used for Microblaze since it doesn't have a native sleep function. To avoid
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* dependency on a hardware timer, the default wait functionality is implemented
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* using loop iterations; this isn't too accurate. If a custom timer handler is
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* used, the user may implement their own wait implementation using a hardware
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* timer (see example/) for better accuracy.
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*
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* @param InstancePtr is a pointer to the XDptx instance.
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* @param MicroSeconds is the number of microseconds to be passed to the
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* timer function.
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*
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* @note None.
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*
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*******************************************************************************/
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typedef void (*XDp_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
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/**************************** Function Prototypes *****************************/
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/* xdp_sinit.c: Configuration extraction function.*/
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XDp_Config *XDp_LookupConfig(u16 DeviceId);
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/******************* Macros (Inline Functions) Definitions ********************/
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#define XDP_TX 0
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#define XDP_RX 1
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/******************************************************************************/
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/**
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* This is function determines whether the DisplayPort core that the
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* configuration structure represents is a transmitter (TX) or a receiver (RX).
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*
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* @param ConfigPtr is a pointer to the DisplayPort core's configuration
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* structure.
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*
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* @return XDP_RX if the configuration structure is for a core of type RX.
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* XDP_TX if the configuration structure is for a core of type TX.
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*
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* @note C-style signature:
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* u32 XDp_CfgGetCoreType(XDp_Config *ConfigPtr)
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*
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*******************************************************************************/
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#define XDp_CfgGetCoreType(ConfigPtr) ((ConfigPtr)->IsRx ? XDP_RX : XDP_TX)
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/******************************* Compatibility ********************************/
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#define XDptx_LookupConfig XDp_LookupConfig
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#define XDptx_Config XDp_Config
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#define XDptx_TimerHandler XDp_TimerHandler
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#include "xdprx.h"
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#include "xdptx.h"
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#endif /* XDP_H_ */
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