167 lines
No EOL
5.6 KiB
C
167 lines
No EOL
5.6 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xaxis_switch_hw.h
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* @addtogroup axis_switch_v1_0
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* @{
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*
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* This header file contains identifiers and register-level core functions (or
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* macros) that can be used to access the Xilinx AXI4-Stream Switch Control
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* Router core.
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*
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* For more information about the operation of this core see the hardware
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* specification and documentation in the higher level driver
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* xaxis_switch.h file.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- --------------------------------------------------
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* 1.00 sha 01/28/15 Initial release.
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* </pre>
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*
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******************************************************************************/
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#ifndef XAXIS_SWITCH_HW_H_
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#define XAXIS_SWITCH_HW_H_ /**< Prevent circular inclusions
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* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name MI MUX register offsets
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*
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* @{
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*/
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#define XAXIS_SCR_CTRL_OFFSET 0x000 /**< Control Register offset */
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#define XAXIS_SCR_MI_MUX_START_OFFSET 0x040 /**< Start of MI MUX Register
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* offset */
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#define XAXIS_SCR_MI_MUX_END_OFFSET 0x07C /**< End of MI MUX Register
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* offset */
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/*@}*/
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/** @name MI MUX Control register mask
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* @{
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*/
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#define XAXIS_SCR_CTRL_REG_UPDATE_MASK 0x02 /**< Register Update
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* mask */
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/*@}*/
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/** @name MI MUX register mask
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*
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* It is applicable for MI[0...15] registers.
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* @{
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*/
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#define XAXIS_SCR_MI_X_MUX_MASK 0x0F /**< MI MUX mask */
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#define XAXIS_SCR_MI_X_DISABLE_MASK 0x80000000 /**< MI Disable mask */
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#define XAXIS_SCR_MI_X_DISABLE_SHIFT 31 /**< MI Disable shift */
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/*@}*/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/** @name Register access macro definition
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* @{
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*/
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#define XAxisScr_In32 Xil_In32 /**< Input Operations */
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#define XAxisScr_Out32 Xil_Out32 /**< Output Operations */
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/*****************************************************************************/
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/**
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*
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* This macro reads a value from a AXI4-Stream Switch register. A 32 bit read
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* is performed. If the component is implemented in a smaller width, only the
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* least significant data is read from the register. The most significant data
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* will be read as 0.
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*
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* @param BaseAddress is the base address of the XAxis_Switch core
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* instance.
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* @param RegOffset is the register offset of the register (defined at
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* the top of this file).
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*
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* @return The 32-bit value of the register.
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*
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* @note C-style signature:
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* u32 XAxisScr_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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******************************************************************************/
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#define XAxisScr_ReadReg(BaseAddress, RegOffset) \
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XAxisScr_In32((BaseAddress) + ((u32)RegOffset))
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/*****************************************************************************/
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/**
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*
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* This macro writes a value to a AXI4-Stream Switch register. A 32 bit write
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* is performed. If the component is implemented in a smaller width, only the
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* least significant data is written.
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*
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* @param BaseAddress is the base address of the XAxis_Switch core
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* instance.
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* @param RegOffset is the register offset of the register (defined at
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* the top of this file) to be written.
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* @param Data is the 32-bit value to write into the register.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XAxisScr_WriteReg(u32 BaseAddress, u32 RegOffset,
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* u32 Data)
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*
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******************************************************************************/
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#define XAxisScr_WriteReg(BaseAddress, RegOffset, Data) \
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XAxisScr_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
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/*@}*/
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/************************** Function Prototypes ******************************/
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/************************** Variable Declarations ****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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/** @} */ |