768 lines
27 KiB
C
768 lines
27 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xcsudma.c
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* @addtogroup csudma_v1_0
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* @{
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* @details
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*
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* This file contains the implementation of the interface functions for CSU_DMA
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* driver. Refer to the header file xcsudma.h for more detailed information.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- ---------------------------------------------------
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* 1.0 vnsld 22/10/14 First release
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xcsudma.h"
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/************************** Function Prototypes ******************************/
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/************************** Function Definitions *****************************/
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/*****************************************************************************/
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/**
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*
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* This function initializes an CSU_DMA core. This function must be called
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* prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting
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* up the instance data and ensuring the hardware is in a quiescent state.
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*
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* @param InstancePtr is a pointer to the XCsuDma instance.
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* @param CfgPtr is a reference to a structure containing information
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* about a specific XCsuDma instance.
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* @param EffectiveAddr is the device base address in the virtual memory
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* address space. The caller is responsible for keeping the
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* address mapping from EffectiveAddr to the device physical
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* base address unchanged once this function is invoked.
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* Unexpected errors may occur if the address mapping changes
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* after this function is called. If address translation is not
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* used, pass in the physical address instead.
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*
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* @return
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* - XST_SUCCESS if initialization was successful.
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*
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* @note None.
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*
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******************************************************************************/
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s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr,
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u32 EffectiveAddr)
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{
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(CfgPtr != NULL);
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Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0));
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/* Setup the instance */
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(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
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sizeof(XCsuDma_Config));
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InstancePtr->Config.BaseAddress = EffectiveAddr;
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XCsuDma_Reset();
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InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
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return (XST_SUCCESS);
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}
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/*****************************************************************************/
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/**
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*
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* This function sets the starting address and amount(size) of the data to be
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* transfered from/to the memory through the AXI interface.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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* @param Addr is a 64 bit variable which holds the starting address of
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* data which needs to write into the memory(DST) (or read from
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* the memory(SRC)).
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* @param Size is a 32 bit variable which represents the number of 4 byte
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* words needs to be transfered from starting address.
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* @param EnDataLast is to trigger an end of message. It will enable or
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* disable data_inp_last signal to stream interface when current
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* command is completed. It is applicable only to source channel
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* and neglected for destination channel.
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* - 1 - Asserts data_inp_last signal.
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* - 0 - data_inp_last will not be asserted.
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*
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* @return None.
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*
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* @note Data_inp_last signal is asserted simultaneously with the
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* data_inp_valid signal associated with the final 32-bit word
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* transfer.
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*
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******************************************************************************/
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void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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UINTPTR Addr, u32 Size, u8 EnDataLast)
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{
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/* Verify arguments */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00);
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Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX));
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Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
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/* Flushing cache memory */
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if (Channel == (XCSUDMA_SRC_CHANNEL)) {
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Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
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}
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/* Invalidating cache memory */
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else {
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Xil_DCacheInvalidateRange(Addr, Size <<
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(u32)(XCSUDMA_SIZE_SHIFT));
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}
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_ADDR_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK)));
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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(((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) &
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(u32)(XCSUDMA_MSB_ADDR_MASK)));
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if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_SIZE_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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((Size << (u32)(XCSUDMA_SIZE_SHIFT)) |
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(u32)(XCSUDMA_LAST_WORD_MASK)));
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}
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else {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_SIZE_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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(Size << (u32)(XCSUDMA_SIZE_SHIFT)));
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}
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}
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/*****************************************************************************/
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/**
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*
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* This function returns the current address location of the memory, from where
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* it has to read the data(SRC) or the location where it has to write the data
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* (DST) based on the channel selection.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return Address is a 64 bit variable which holds the current address.
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* - From this location data has to be read(SRC)
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* - At this location data has to be written(DST)
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*
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* @note None.
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*
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******************************************************************************/
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u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
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{
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u64 FullAddr;
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/* Verify arguments */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_ADDR_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
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FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_ADDR_MSB_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) <<
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(u64)(XCSUDMA_MSB_ADDR_SHIFT));
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return FullAddr;
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}
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/*****************************************************************************/
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/**
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*
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* This function returns the size of the data yet to be transfered from memory
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* to CSU_DMA or CSU_DMA to memory based on the channel selection.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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*
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* @return Size is amount of data yet to be transfered.
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*
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* @note None.
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*
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******************************************************************************/
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u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel)
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{
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u32 Size;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_SIZE_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >>
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(u32)(XCSUDMA_SIZE_SHIFT);
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return Size;
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}
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/*****************************************************************************/
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/**
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*
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* This function pause the Channel data tranfer to/from memory or to/from stream
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* based on pause type.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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* @param Type is type of the pause to be enabled.
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* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
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* - SRC Stops issuing of new read commands to memory.
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* - DST Stops issuing of new write commands to memory.
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* - XCSUDMA_PAUSE_STREAM(1) - Pause stream
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* - SRC Stops transfer of data from FIFO to Stream.
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* - DST Stops transfer of data from stream to FIFO.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_PauseType Type)
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{
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
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(Type == (XCSUDMA_PAUSE_STREAM)));
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Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
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/* Pause Memory Read/Write/Stream operations */
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if (Type == (XCSUDMA_PAUSE_MEMORY)) {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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(XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) |
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(u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)));
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}
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if (Type == (XCSUDMA_PAUSE_STREAM)) {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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(XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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(Channel * (u32)XCSUDMA_OFFSET_DIFF))) |
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(u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)));
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}
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}
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/*****************************************************************************/
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/**
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*
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* This functions checks whether Channel's memory or stream is paused or not
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* based on the given pause type.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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* @param Type is type of the pause which needs to be checked.
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* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
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* - SRC Stops issuing of new read commands to memory.
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* - DST Stops issuing of new write commands to memory.
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* - XCSUDMA_PAUSE_STREAM(1) - Pause stream
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* - SRC Stops transfer of data from FIFO to Stream.
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* - DST Stops transfer of data from stream to FIFO.
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*
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* @return Returns the pause status.
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* - TRUE if it is in paused state.
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* - FALSE if it is not in pause state.
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*
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* @note None.
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*
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******************************************************************************/
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s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_PauseType Type)
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{
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u32 Data;
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s32 PauseState;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
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(Type == (XCSUDMA_PAUSE_STREAM)));
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Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
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/* To know Pause condition of Memory Read/Write/Stream operations */
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if (Type == (XCSUDMA_PAUSE_MEMORY)) {
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if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) ==
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(u32)0x00) {
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PauseState = (s32)(FALSE);
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}
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else {
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PauseState = (s32)(TRUE);
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}
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}
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else {
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if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) ==
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(u32)0x00) {
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PauseState = (s32)(FALSE);
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}
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else {
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PauseState = (s32)(TRUE);
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}
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}
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return (s32)PauseState;
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}
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/*****************************************************************************/
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/**
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*
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* This function resumes the channel if it is in paused state and continues
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* where it has left or no effect if it is not in paused state, based on the
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* type of pause.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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* @param Channel represents the type of channel either it is Source or
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* Destination.
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* Source channel - XCSUDMA_SRC_CHANNEL
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* Destination Channel - XCSUDMA_DST_CHANNEL
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* @param Type is type of the pause to be Resume if it is in pause
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* state.
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* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory
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* - SRC Stops issuing of new read commands to memory.
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* - DST Stops issuing of new write commands to memory.
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* - XCSUDMA_PAUSE_STREAM(1) - Pause stream
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* - SRC Stops transfer of data from FIFO to Stream.
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* - DST Stops transfer of data from stream to FIFO.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
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XCsuDma_PauseType Type)
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{
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u32 Data;
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) ||
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(Type == (XCSUDMA_PAUSE_STREAM)));
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Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
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(Channel == (XCSUDMA_DST_CHANNEL)));
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Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
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Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
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if (Type == (XCSUDMA_PAUSE_MEMORY)) {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))),
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(Data &
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(~(XCSUDMA_CTRL_PAUSE_MEM_MASK))));
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}
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if (Type == (XCSUDMA_PAUSE_STREAM)) {
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XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
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((u32)(XCSUDMA_CTRL_OFFSET) +
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(((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))),
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( Data &
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(~(XCSUDMA_CTRL_PAUSE_STRM_MASK))));
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}
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}
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/*****************************************************************************/
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/**
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*
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* This function returns the sum of all the data read from AXI memory. It is
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* valid only one we use CSU_DMA source channel.
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*
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* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
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*
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* @return Returns the sum of all the data read from memory.
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*
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* @note Before start of the transfer need to clear this register to get
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* correct sum otherwise it adds to previous value which results
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* to wrong output.
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* Valid only for source channel
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*
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******************************************************************************/
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u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr)
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{
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u32 ChkSum;
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady ==
|
|
(u32)(XIL_COMPONENT_IS_READY));
|
|
|
|
ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
|
|
(u32)(XCSUDMA_CRC_OFFSET));
|
|
|
|
return ChkSum;
|
|
|
|
}
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This function clears the check sum of the data read from AXI memory. It is
|
|
* valid only for CSU_DMA source channel.
|
|
*
|
|
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
|
|
*
|
|
* @return Returns the sum of all the data read from memory.
|
|
*
|
|
* @note Before start of the transfer need to clear this register to get
|
|
* correct sum otherwise it adds to previous value which results
|
|
* to wrong output.
|
|
*
|
|
******************************************************************************/
|
|
void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr)
|
|
{
|
|
|
|
/* Verify arguments. */
|
|
Xil_AssertVoid(InstancePtr != NULL);
|
|
|
|
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
|
|
(u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK));
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* This function cofigures all the values of CSU_DMA's Channels with the values
|
|
* of updated XCsuDma_Configure structure.
|
|
*
|
|
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
|
|
* @param Channel represents the type of channel either it is Source or
|
|
* Destination.
|
|
* Source channel - XCSUDMA_SRC_CHANNEL
|
|
* Destination Channel - XCSUDMA_DST_CHANNEL
|
|
* @param ConfigurValues is a pointer to the structure XCsuDma_Configure
|
|
* whose values are used to configure CSU_DMA core.
|
|
* - SssFifoThesh When the DST FIFO level >= this value,
|
|
* the SSS interface signal, "data_out_fifo_level_hit" will be
|
|
* asserted. This mechanism can be used by the SSS to flow
|
|
* control data that is being looped back from the SRC DMA.
|
|
* - Range is (0x10 to 0x7A) threshold is 17 to 123
|
|
* entries.
|
|
* - It is valid only for DST CSU_DMA IP.
|
|
* - ApbErr When accessed to invalid APB the resulting
|
|
* pslerr will be
|
|
* - 0 - 1'b0
|
|
* - 1 - 1'b1
|
|
* - EndianType Type of endianness
|
|
* - 0 doesn't change order
|
|
* - 1 will flip the order.
|
|
* - AxiBurstType....Type of the burst
|
|
* - 0 will issue INCR type burst
|
|
* - 1 will issue FIXED type burst
|
|
* - TimeoutValue Time out value for timers
|
|
* - 0x000 to 0xFFE are valid inputs
|
|
* - 0xFFF clears both timers
|
|
* - FifoThresh......Programmed watermark value
|
|
* - Range is 0x00 to 0x80 (0 to 128 entries).
|
|
* - Acache Sets the AXI CACHE bits on the AXI Write/Read
|
|
* channel.
|
|
* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
|
|
* for DST channel are always 1, we need to configure
|
|
* remaining 3 signal support
|
|
* (Bufferable, Read allocate and Write allocate).
|
|
* Valid inputs are:
|
|
* - 0x000 - Cacheable, but do not allocate
|
|
* - 0x001 - Cacheable and bufferable, but do not allocate
|
|
* - 0x010 - Cacheable write-through, allocate on reads
|
|
* only
|
|
* - 0x011 - Cacheable write-back, allocate on reads only
|
|
* - 0x100 - Cacheable write-through, allocate on writes
|
|
* only
|
|
* - 0x101 - Cacheable write-back, allocate on writes only
|
|
* - 0x110 - Cacheable write-through, allocate on both
|
|
* reads and writes
|
|
* - 0x111 - Cacheable write-back, allocate on both reads
|
|
* and writes
|
|
* - RouteBit To select route
|
|
* - 0 : Command will be routed normally
|
|
* - 1 : Command will be routed to APU's cache controller
|
|
* - TimeoutEn To enable or disable time out counters
|
|
* - 0 : The 2 Timeout counters are disabled
|
|
* - 1 : The 2 Timeout counters are enabled
|
|
* - TimeoutPre Set the prescaler value for the timeout in
|
|
* clk (~2.5ns) cycles
|
|
* - Range is 0x000(Prescaler enables timer every cycles)
|
|
* to 0xFFF(Prescaler enables timer every 4096 cycles)
|
|
* - MaxOutCmds Controls the maximumum number of outstanding
|
|
* AXI read commands issued.
|
|
* - Range is 0x0(Up to 1 Outstanding Read command
|
|
* allowed) to 0x8 (Up to 9 Outstanding Read
|
|
* command allowed)
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note To use timers timeout value Timeout enable field should be
|
|
* enabled.
|
|
*
|
|
******************************************************************************/
|
|
void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
|
|
XCsuDma_Configure *ConfigurValues)
|
|
{
|
|
u32 Data;
|
|
|
|
/* Verify arguments. */
|
|
Xil_AssertVoid(InstancePtr != NULL);
|
|
Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY));
|
|
Xil_AssertVoid(ConfigurValues != NULL);
|
|
Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
|
|
(Channel == (XCSUDMA_DST_CHANNEL)));
|
|
Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE));
|
|
|
|
Data = (((ConfigurValues->EndianType <<
|
|
(u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL_ENDIAN_MASK)) |
|
|
((ConfigurValues->ApbErr <<
|
|
(u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL_APB_ERR_MASK)) |
|
|
((ConfigurValues->AxiBurstType <<
|
|
(u32)(XCSUDMA_CTRL_BURST_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL_BURST_MASK)) |
|
|
((ConfigurValues->TimeoutValue <<
|
|
(u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) |
|
|
((ConfigurValues->FifoThresh <<
|
|
(u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)));
|
|
if(Channel == XCSUDMA_DST_CHANNEL) {
|
|
Data = Data | (u32)((ConfigurValues->SssFifoThesh <<
|
|
(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK));
|
|
}
|
|
|
|
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
|
|
((u32)(XCSUDMA_CTRL_OFFSET) +
|
|
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
|
|
|
|
Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
|
|
((u32)(XCSUDMA_CTRL2_OFFSET) +
|
|
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) &
|
|
(u32)(XCSUDMA_CTRL2_RESERVED_MASK));
|
|
Data |= (((ConfigurValues->Acache <<
|
|
(u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL2_ACACHE_MASK)) |
|
|
((ConfigurValues->RouteBit <<
|
|
(u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL2_ROUTE_MASK)) |
|
|
((ConfigurValues->TimeoutEn <<
|
|
(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) |
|
|
((ConfigurValues->TimeoutPre <<
|
|
(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) &
|
|
(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) |
|
|
((ConfigurValues->MaxOutCmds) &
|
|
(u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
|
|
|
|
XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
|
|
((u32)(XCSUDMA_CTRL2_OFFSET) +
|
|
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This function updates XCsuDma_Configure structure members with the cofigured
|
|
* values of CSU_DMA's Channel.
|
|
*
|
|
* @param InstancePtr is a pointer to XCsuDma instance to be worked on.
|
|
* @param Channel represents the type of channel either it is Source or
|
|
* Destination.
|
|
* Source channel - XCSUDMA_SRC_CHANNEL
|
|
* Destination Channel - XCSUDMA_DST_CHANNEL
|
|
* @param ConfigurValues is a pointer to the structure XCsuDma_Configure
|
|
* whose members are updated with configurations of CSU_DMA core.
|
|
* - SssFifoThesh When the DST FIFO level >= this value,
|
|
* the SSS interface signal, "data_out_fifo_level_hit" will be
|
|
* asserted. This mechanism can be used by the SSS to flow
|
|
* control data that is being looped back from the SRC DMA.
|
|
* - Range is (0x10 to 0x7A) threshold is 17 to 123
|
|
* entries.
|
|
* - It is valid only for DST CSU_DMA IP.
|
|
* - ApbErr When accessed to invalid APB the resulting
|
|
* pslerr will be
|
|
* - 0 - 1'b0
|
|
* - 1 - 1'b1
|
|
* - EndianType Type of endianness
|
|
* - 0 doesn't change order
|
|
* - 1 will flip the order.
|
|
* - AxiBurstType....Type of the burst
|
|
* - 0 will issue INCR type burst
|
|
* - 1 will issue FIXED type burst
|
|
* - TimeoutValue Time out value for timers
|
|
* - 0x000 to 0xFFE are valid inputs
|
|
* - 0xFFF clears both timers
|
|
* - FifoThresh......Programmed watermark value
|
|
* - Range is 0x00 to 0x80 (0 to 128 entries).
|
|
* - Acache Sets the AXI CACHE bits on the AXI Write/Read
|
|
* channel.
|
|
* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1]
|
|
* for DST channel are always 1, we need to configure
|
|
* remaining 3 signal support
|
|
* (Bufferable, Read allocate and Write allocate).
|
|
* Valid inputs are:
|
|
* - 0x000 - Cacheable, but do not allocate
|
|
* - 0x001 - Cacheable and bufferable, but do not allocate
|
|
* - 0x010 - Cacheable write-through, allocate on reads
|
|
* only
|
|
* - 0x011 - Cacheable write-back, allocate on reads only
|
|
* - 0x100 - Cacheable write-through, allocate on writes
|
|
* only
|
|
* - 0x101 - Cacheable write-back, allocate on writes only
|
|
* - 0x110 - Cacheable write-through, allocate on both
|
|
* reads and writes
|
|
* - 0x111 - Cacheable write-back, allocate on both reads
|
|
* and writes
|
|
* - RouteBit To select route
|
|
* - 0 : Command will be routed based normally
|
|
* - 1 : Command will be routed to APU's cache controller
|
|
* - TimeoutEn To enable or disable time out counters
|
|
* - 0 : The 2 Timeout counters are disabled
|
|
* - 1 : The 2 Timeout counters are enabled
|
|
* - TimeoutPre Set the prescaler value for the timeout in
|
|
* clk (~2.5ns) cycles
|
|
* - Range is 0x000(Prescaler enables timer every cycles)
|
|
* to 0xFFF(Prescaler enables timer every 4096 cycles)
|
|
* - MaxOutCmds Controls the maximumum number of outstanding
|
|
* AXI read commands issued.
|
|
* - Range is 0x0(Up to 1 Outstanding Read command
|
|
* allowed) to 0x8 (Up to 9 Outstanding Read command
|
|
* allowed)
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note None.
|
|
*
|
|
******************************************************************************/
|
|
void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
|
|
XCsuDma_Configure *ConfigurValues)
|
|
{
|
|
u32 Data;
|
|
|
|
/* Verify arguments. */
|
|
Xil_AssertVoid(InstancePtr != NULL);
|
|
Xil_AssertVoid(ConfigurValues != NULL);
|
|
Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) ||
|
|
(Channel == (XCSUDMA_DST_CHANNEL)));
|
|
|
|
Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
|
|
((u32)(XCSUDMA_CTRL_OFFSET) +
|
|
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
|
|
|
|
if (Channel == (XCSUDMA_DST_CHANNEL)) {
|
|
ConfigurValues->SssFifoThesh =
|
|
(u8)((Data &
|
|
(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT));
|
|
}
|
|
ConfigurValues->ApbErr =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL_APB_ERR_SHIFT));
|
|
ConfigurValues->EndianType =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL_ENDIAN_SHIFT));
|
|
ConfigurValues->AxiBurstType =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL_BURST_SHIFT));
|
|
ConfigurValues->TimeoutValue =
|
|
((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT));
|
|
ConfigurValues->FifoThresh =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT));
|
|
|
|
Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress,
|
|
((u32)(XCSUDMA_CTRL2_OFFSET) +
|
|
((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))));
|
|
|
|
ConfigurValues->Acache =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL2_ACACHE_SHIFT));
|
|
ConfigurValues->RouteBit =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL2_ROUTE_SHIFT));
|
|
ConfigurValues->TimeoutEn =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT));
|
|
ConfigurValues->TimeoutPre =
|
|
(u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >>
|
|
(u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT));
|
|
ConfigurValues->MaxOutCmds =
|
|
(u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK)));
|
|
|
|
}
|
|
/** @} */
|