embeddedsw/XilinxProcessorIPLib/drivers/vprocss/src/xvprocss_g.c
Rohit Consul 478171fa76 vprocss: Align with SSW coding guidelines and few bug fixes
-Updated driver structure, variable and API names to align with
 defined coding guidelines
-Load scalers and chroma resampler coefficients only if the
 instantiated configuration supports it

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
2015-08-24 23:09:53 +05:30

145 lines
4.6 KiB
C

/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
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*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
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* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
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*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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*Except as contained in this notice, the name of the Xilinx shall not be used
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*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xvprocss.h"
/*
* List of Sub-cores included in the subsystem
* Sub-core device id will be set by its driver in xparameters.h
*/
#define XPAR_V_PROC_SS_0_AXI_VDMA_PRESENT 1
#define XPAR_V_PROC_SS_0_RESET_SEL_AXI_MM_PRESENT 1
#define XPAR_V_PROC_SS_0_RESET_SEL_AXIS_PRESENT 1
#define XPAR_V_PROC_SS_0_V_CSC_PRESENT 1
#define XPAR_V_PROC_SS_0_V_DEINTERLACER_PRESENT 1
#define XPAR_V_PROC_SS_0_V_HCRESAMPLER_PRESENT 1
#define XPAR_V_PROC_SS_0_V_HSCALER_PRESENT 1
#define XPAR_V_PROC_SS_0_V_LETTERBOX_PRESENT 1
#define XPAR_V_PROC_SS_0_V_VCRESAMPLER_IN_PRESENT 1
#define XPAR_V_PROC_SS_0_V_VCRESAMPLER_OUT_PRESENT 1
#define XPAR_V_PROC_SS_0_V_VSCALER_PRESENT 1
#define XPAR_V_PROC_SS_0_VIDEO_ROUTER_XBAR_PRESENT 1
/*
* List of Sub-cores excluded from the subsystem
* - Excluded sub-core device id is set to 255
* - Excluded sub-core baseaddr is set to 0
*/
XVprocSs_Config XVprocSs_ConfigTable[] =
{
{
XPAR_V_PROC_SS_0_DEVICE_ID,
XPAR_V_PROC_SS_0_BASEADDR,
XPAR_V_PROC_SS_0_HIGHADDR,
XPAR_V_PROC_SS_0_TOPOLOGY,
XPAR_V_PROC_SS_0_SAMPLES_PER_CLK,
XPAR_V_PROC_SS_0_MAX_DATA_WIDTH,
XPAR_V_PROC_SS_0_NUM_VIDEO_COMPONENTS,
XPAR_V_PROC_SS_0_MAX_COLS,
XPAR_V_PROC_SS_0_MAX_ROWS,
{
XPAR_V_PROC_SS_0_RESET_SEL_AXI_MM_PRESENT,
XPAR_V_PROC_SS_0_RESET_SEL_AXI_MM_DEVICE_ID,
XPAR_V_PROC_SS_0_RESET_SEL_AXI_MM_BASEADDR
},
{
XPAR_V_PROC_SS_0_RESET_SEL_AXIS_PRESENT,
XPAR_V_PROC_SS_0_RESET_SEL_AXIS_DEVICE_ID,
XPAR_V_PROC_SS_0_RESET_SEL_AXIS_BASEADDR
},
{
XPAR_V_PROC_SS_0_AXI_VDMA_PRESENT,
XPAR_V_PROC_SS_0_AXI_VDMA_DEVICE_ID,
XPAR_V_PROC_SS_0_AXI_VDMA_BASEADDR
},
{
XPAR_V_PROC_SS_0_VIDEO_ROUTER_XBAR_PRESENT,
XPAR_V_PROC_SS_0_VIDEO_ROUTER_XBAR_DEVICE_ID,
XPAR_V_PROC_SS_0_VIDEO_ROUTER_XBAR_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_CSC_PRESENT,
XPAR_V_PROC_SS_0_V_CSC_DEVICE_ID,
XPAR_V_PROC_SS_0_V_CSC_S_AXI_CTRL_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_DEINTERLACER_PRESENT,
XPAR_V_PROC_SS_0_V_DEINTERLACER_DEVICE_ID,
XPAR_V_PROC_SS_0_V_DEINTERLACER_S_AXI_CTRL_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_HCRESAMPLER_PRESENT,
XPAR_V_PROC_SS_0_V_HCRESAMPLER_DEVICE_ID,
XPAR_V_PROC_SS_0_V_HCRESAMPLER_S_AXI_CTRL_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_HSCALER_PRESENT,
XPAR_V_PROC_SS_0_V_HSCALER_DEVICE_ID,
XPAR_V_PROC_SS_0_V_HSCALER_S_AXI_CTRL_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_LETTERBOX_PRESENT,
XPAR_V_PROC_SS_0_V_LETTERBOX_DEVICE_ID,
XPAR_V_PROC_SS_0_V_LETTERBOX_S_AXI_CTRL_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_VCRESAMPLER_IN_PRESENT,
XPAR_V_PROC_SS_0_V_VCRESAMPLER_IN_DEVICE_ID,
XPAR_V_PROC_SS_0_V_VCRESAMPLER_IN_S_AXI_CTRL_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_VCRESAMPLER_OUT_PRESENT,
XPAR_V_PROC_SS_0_V_VCRESAMPLER_OUT_DEVICE_ID,
XPAR_V_PROC_SS_0_V_VCRESAMPLER_OUT_S_AXI_CTRL_BASEADDR
},
{
XPAR_V_PROC_SS_0_V_VSCALER_PRESENT,
XPAR_V_PROC_SS_0_V_VSCALER_DEVICE_ID,
XPAR_V_PROC_SS_0_V_VSCALER_S_AXI_CTRL_BASEADDR
},
}
};