2dee01e56d
This patch updates the standalone files copyright information with the latest content. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
211 lines
7 KiB
ArmAsm
211 lines
7 KiB
ArmAsm
/******************************************************************************
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*
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* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* microblaze_scrub ()
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*
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* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
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* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
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* of an uncorrectable error when fault tolerance support is enabled.
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*
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* This routine assumes that the processor is in privileged mode when it is
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* called, if the MMU is enabled.
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*
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* Call this routine regularly from a timer interrupt.
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*
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* Parameters:
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* None
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*
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*
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*******************************************************************************/
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#include "xparameters.h"
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/* Define if fault tolerance is used */
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#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
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#if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
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#define FAULT_TOLERANT
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#endif
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#endif
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/* Define if LMB is used and can be scrubbed */
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#if defined(XPAR_MICROBLAZE_D_LMB) && \
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defined(XPAR_DLMB_CNTLR_BASEADDR) && \
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defined(XPAR_DLMB_CNTLR_HIGHADDR)
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#if XPAR_MICROBLAZE_D_LMB == 1
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#define HAS_SCRUBBABLE_LMB
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#define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
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#endif
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#endif
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/* Set default cache line lengths */
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#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
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#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
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#endif
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#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
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#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
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#endif
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/* Define if internal Data Cache BRAMs are used */
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#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
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#if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
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#define HAS_BRAM_DCACHE
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#define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
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#define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
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#endif
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#endif
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/* Define if internal Instruction Cache BRAMs are used */
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#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
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#if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
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#define HAS_BRAM_ICACHE
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#define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
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#define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
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#endif
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#endif
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/* Define if internal MMU UTLB BRAM is used */
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#ifdef XPAR_MICROBLAZE_USE_MMU
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#if XPAR_MICROBLAZE_USE_MMU > 1
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#define HAS_BRAM_MMU_UTLB
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#endif
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#endif
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/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
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#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
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defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
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#if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
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#if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
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XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
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#define HAS_BRAM_BRANCH_TARGET_CACHE
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#ifdef HAS_BRAM_DCACHE
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#define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
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#else
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#define BTC_MASK_D 256
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#endif
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#ifdef HAS_BRAM_ICACHE
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#define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
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#else
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#define BTC_MASK_I 256
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#endif
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#if BTC_MASK_D > BTC_MASK_I
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#define BTC_MASK BTC_MASK_D
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#else
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#define BTC_MASK BTC_MASK_I
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#endif
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#endif
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#endif
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#endif
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/* Define index offsets to persistent data used by this routine */
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#define DLMB_INDEX_OFFSET 0
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#define DCACHE_INDEX_OFFSET 4
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#define ICACHE_INDEX_OFFSET 8
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#define MMU_INDEX_OFFSET 12
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#define BTC_CALL_COUNT_OFFSET 16
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.text
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.globl microblaze_scrub
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.ent microblaze_scrub
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.align 2
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microblaze_scrub:
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#ifdef FAULT_TOLERANT
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la r6, r0, L_persistent_data /* Get pointer to data */
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#ifdef HAS_SCRUBBABLE_LMB
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L_dlmb:
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lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
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lw r7, r5, r0 /* Load and store */
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sw r7, r5, r0
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addik r5, r5, 4 /* Increment and save dlmb index */
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andi r5, r5, DLMB_MASK
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swi r5, r6, DLMB_INDEX_OFFSET
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#endif /* HAS_SCRUBBABLE_LMB */
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#ifdef HAS_BRAM_DCACHE
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L_dcache:
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lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
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wdc r5, r0 /* Invalidate data cache line */
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addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
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andi r5, r5, DCACHE_MASK
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swi r5, r6, DCACHE_INDEX_OFFSET
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#endif /* HAS_BRAM_DCACHE */
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#ifdef HAS_BRAM_ICACHE
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L_icache:
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lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
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wic r5, r0 /* Invalidate data cache line */
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addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
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andi r5, r5, ICACHE_MASK
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swi r5, r6, ICACHE_INDEX_OFFSET
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#endif /* HAS_BRAM_ICACHE */
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#ifdef HAS_BRAM_MMU_UTLB
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L_mmu:
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lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
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mts rtlbx, r5 /* Access next entry in UTLB */
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mts rtlbhi, r0 /* Clear the UTLB entry */
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addik r5, r5, 1 /* Increment and save entry index */
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andi r5, r5, 0x3F
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swi r5, r6, MMU_INDEX_OFFSET
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#endif /* HAS_BRAM_MMU_UTLB */
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#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
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L_btc:
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lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
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addik r5, r5, 1 /* Increment and save call count */
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andi r5, r5, BTC_MASK
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swi r5, r6, BTC_CALL_COUNT_OFFSET
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bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
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bri 4 /* Clear branch target cache */
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L_skip_btc_scrub:
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#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
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#endif /* FAULT_TOLERANT */
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L_done:
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rtsd r15, 8 /* Return */
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nop
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.end microblaze_scrub
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/* Persistent data used by this routine */
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.data
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.align 2
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L_persistent_data:
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.long 0 /* dlmb index */
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.long 0 /* dcache index */
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.long 0 /* icache index */
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.long 0 /* mmu entry index */
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.long 0 /* btc call count */
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