0ae197d5e4
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Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
183 lines
4.5 KiB
C
183 lines
4.5 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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#if __MICROBLAZE__ || __PPC__
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#include "arch/cc.h"
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#include "platform.h"
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#include "platform_config.h"
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#include "xil_cache.h"
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#include "xparameters.h"
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#include "xintc.h"
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#include "xil_exception.h"
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#include "lwip/tcp.h"
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#ifdef STDOUT_IS_16550
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#include "xuartns550_l.h"
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#endif
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#include "lwip/tcp.h"
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#if LWIP_DHCP==1
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volatile int dhcp_timoutcntr = 24;
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void dhcp_fine_tmr();
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void dhcp_coarse_tmr();
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#endif
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volatile int TcpFastTmrFlag = 0;
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volatile int TcpSlowTmrFlag = 0;
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void
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timer_callback()
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{
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/* we need to call tcp_fasttmr & tcp_slowtmr at intervals specified by lwIP.
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* It is not important that the timing is absoluetly accurate.
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*/
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static int odd = 1;
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#if LWIP_DHCP==1
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static int dhcp_timer = 0;
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#endif
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TcpFastTmrFlag = 1;
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odd = !odd;
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if (odd) {
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#if LWIP_DHCP==1
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dhcp_timer++;
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dhcp_timoutcntr--;
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#endif
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TcpSlowTmrFlag = 1;
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#if LWIP_DHCP==1
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dhcp_fine_tmr();
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if (dhcp_timer >= 120) {
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dhcp_coarse_tmr();
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dhcp_timer = 0;
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}
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#endif
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}
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}
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static XIntc intc;
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void platform_setup_interrupts()
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{
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XIntc *intcp;
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intcp = &intc;
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XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
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XIntc_Start(intcp, XIN_REAL_MODE);
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/* Start the interrupt controller */
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XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
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#ifdef __PPC__
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Xil_ExceptionInit();
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Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
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(XExceptionHandler)XIntc_DeviceInterruptHandler,
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(void*) XPAR_INTC_0_DEVICE_ID);
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#elif __MICROBLAZE__
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microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
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#endif
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platform_setup_timer();
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#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
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/* Enable timer and EMAC interrupts in the interrupt controller */
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XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
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#ifdef __MICROBLAZE__
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PLATFORM_TIMER_INTERRUPT_MASK |
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#endif
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XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
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#endif
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#ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID
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#ifdef __MICROBLAZE__
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XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
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#endif
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XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);
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#endif
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#ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID
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XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
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XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID);
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#endif
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#ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID
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#ifdef __MICROBLAZE__
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XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
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#endif
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XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID);
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#endif
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}
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void
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enable_caches()
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{
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#ifdef __PPC__
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Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
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Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
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#elif __MICROBLAZE__
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#ifdef XPAR_MICROBLAZE_USE_ICACHE
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Xil_ICacheEnable();
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#endif
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#ifdef XPAR_MICROBLAZE_USE_DCACHE
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Xil_DCacheEnable();
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#endif
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#endif
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}
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void
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disable_caches()
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{
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Xil_DCacheDisable();
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Xil_ICacheDisable();
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}
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void init_platform()
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{
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enable_caches();
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#ifdef STDOUT_IS_16550
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XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
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XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
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#endif
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platform_setup_interrupts();
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}
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void cleanup_platform()
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{
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disable_caches();
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}
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#endif
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