2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
319 lines
9.9 KiB
C
Executable file
319 lines
9.9 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xtrafgen_streamingmaster_example.c
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*
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* This file demonstrates how to use the xtrafgen driver on the Xilinx AXI
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* Traffic Generator core. The AXI Traffic Generator IP is designed to
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* generate AXI4 traffic which can be used to stress different modules/
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* interconnect connected in the system.
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*
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* This example demonstrates how to use Streaming mode in Axi Traffic Genrator
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* When Configured in Master only mode.In this mode the core genrates Streaming
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* Traffic based on the transfer length and transfer count configured.
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* To test this example hardware Must contain a Streaming FIFO and the
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* Connections To Axi TrafficGen needs to made As shown below
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* ________________
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* ____________ _________|AXI_STR_RXD |
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* | | | | |
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* | |_____| | |
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* | axi_master| |________________|
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* |____________|
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*
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* Axi TrafficGen Axi Stream FIFO
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*
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*<pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.01a adk 03/09/13 First release
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* 2.00a adk 16/09/13 Fixed CR:737291
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* 2.01a adk 15/11/13 Fixed CR:760808
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*
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* </pre>
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*
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* ***************************************************************************
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*/
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/***************************** Include Files *********************************/
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#include "xtrafgen.h"
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#include "xparameters.h"
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#include "xil_exception.h"
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#include "xllfifo.h"
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#ifdef XPAR_UARTNS550_0_BASEADDR
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#include "xuartns550_l.h" /* to use uartns550 */
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#endif
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define TRAFGEN_DEV_ID XPAR_AXI_TRAFFIC_GEN_2_DEVICE_ID
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#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_V6DDR_0_S_AXI_BASEADDR
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#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_S6DDR_0_S0_AXI_BASEADDR
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#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#elif XPAR_MIG7SERIES_0_BASEADDR
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#define DDR_BASE_ADDR XPAR_MIG_1_BASEADDR
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#endif
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#ifndef DDR_BASE_ADDR
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#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
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DEFAULT SET TO 0x01000000
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#define MEM_BASE_ADDR 0x01000000
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#else
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#define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000)
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#endif
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#define BURST_LEN 255
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#define STR_FIFO0_ADDR XPAR_AXI_FIFO_0_BASEADDR
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#undef DEBUG
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/************************** Function Prototypes ******************************/
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int XTrafGenStremingModeMasterExample(XTrafGen *InstancePtr, u16 DeviceId);
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#ifdef XPAR_UARTNS550_0_BASEADDR
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static void Uart550_Setup(void);
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#endif
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/************************** Variable Definitions *****************************/
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/*
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* Device instance definitions
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*/
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XTrafGen XTrafGenInstance;
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XLlFifo XLlFifoInstance;
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/*****************************************************************************/
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/**
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*
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* Main function
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*
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* This function is the main entry of the traffic generator test.
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*
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* @param None
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*
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* @return - XST_SUCCESS if tests pass
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* - XST_FAILURE if fails.
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*
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* @note None.
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*
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******************************************************************************/
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int main()
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{
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int Status;
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xil_printf("--- Entering main() ---\n\r");
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Status = XTrafGenStremingModeMasterExample(&XTrafGenInstance,
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TRAFGEN_DEV_ID);
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if (Status != XST_SUCCESS) {
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xil_printf("Traffic Gen Streaming Example Test Failed\n\r");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_FAILURE;
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}
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xil_printf("Traffic Gen Streaming Example Test passed\n\r");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* This function demonstrates the usage Traffic Generator
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* It does the following:
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* - Set up the output terminal if UART16550 is in the hardware build
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* - Initialize the AXI Traffic Generator device
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* - Initialize the Streaming FIFO device
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* - Set the Desired Transfer Count and Transfer Length
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* - Enable the Traffic Genration on the Core
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* - Check for the Streaming data on the FIFO
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* - Return test status and exit
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*
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* @param InstancePtr is a pointer to the instance of the
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* XTrafGen component.
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* @param DeviceId is Device ID of the Axi Traffic Generator Device,
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*
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*
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* @param InstancePtr is a pointer to the instance of the
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* XTrafGen component.
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* @param DeviceId is Device ID of the Axi Traffic Generator Device,
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* typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
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* xparameters.h.
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*
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* @return -XST_SUCCESS to indicate success
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* -XST_FAILURE to indicate failure
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*
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******************************************************************************/
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int XTrafGenStremingModeMasterExample(XTrafGen *InstancePtr, u16 DeviceId)
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{
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XTrafGen_Config *Config;
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int Status = XST_SUCCESS;
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u32 Len;
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u32 TransferCnt;
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u32 AtgPacket;
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u32 FifoOcy;
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u32 FifoLen;
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/* Initial setup for Uart16550 */
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#ifdef XPAR_UARTNS550_0_BASEADDR
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Uart550_Setup();
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#endif
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/* Initialize the Device Configuration Interface driver */
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Config = XTrafGen_LookupConfig(DeviceId);
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if (!Config) {
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xil_printf("No config found for %d\r\n", DeviceId);
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return XST_FAILURE;
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}
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/*
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* This is where the virtual address would be used, this example
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* uses physical address.
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*/
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Status = XTrafGen_CfgInitialize(InstancePtr, Config,
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Config->BaseAddress);
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if (Status != XST_SUCCESS) {
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xil_printf("Initialization failed\n\r");
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return Status;
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}
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/* Check for the Streaming Mode */
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if(InstancePtr->OperatingMode != XTG_MODE_STREAMING) {
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return XST_FAILURE;
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}
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/* Initialize the Fifo Instance */
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XLlFifo_Initialize(&XLlFifoInstance , STR_FIFO0_ADDR);
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Status = XLlFifo_Status(&XLlFifoInstance);
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XLlFifo_IntClear(&XLlFifoInstance,0xffffffff);
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Status = XLlFifo_Status(&XLlFifoInstance);
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if(Status != 0x0) {
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xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
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"Expected : 0x0\n\r",
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XLlFifo_Status(&XLlFifoInstance));
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return XST_FAILURE;
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}
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/*
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* Set the Required trasaction length
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* and required transaction count
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*/
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XTrafGen_ResetStreamingRandomLen(InstancePtr);
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XTrafGen_SetStreamingTransLen(InstancePtr , 3);
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XTrafGen_SetStreamingTransCnt(InstancePtr , 2);
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Len = XTrafGen_GetStreamingTransLen(InstancePtr);
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TransferCnt = XTrafGen_GetStreamingTransCnt(InstancePtr);
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/*
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* Calculate the ATG data that is sent on the
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* CORE when Streaming is Enabled
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*/
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AtgPacket = (Len +1) * TransferCnt;
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/* Enable the traffic genration */
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XTrafGen_StreamEnable(InstancePtr);
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FifoOcy = XLlFifo_iRxOccupancy(&XLlFifoInstance);
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if(FifoOcy != AtgPacket) {
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xil_printf("\n ERROR : Not received complete packets : 0x%x \t"
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"Expected : 0x%x \n\r",
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XLlFifo_iRxOccupancy(&XLlFifoInstance), AtgPacket);
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return XST_FAILURE;
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}
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FifoLen = XLlFifo_iRxGetLen(&XLlFifoInstance);
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if(FifoLen != (AtgPacket*4/TransferCnt)) {
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xil_printf("\n ERROR : Not received complete bytes : 0x%x \t"
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"Expected : 0x%x \n\n\r",
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XLlFifo_iRxGetLen(&XLlFifoInstance),Len);
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return XST_FAILURE;
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}
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while(XLlFifo_iRxGetLen(&XLlFifoInstance)) {
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xil_printf("Recived packet DATA: 0x%x \n\r",
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XLlFifo_RxGetWord(&XLlFifoInstance));
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}
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if(XLlFifo_iRxOccupancy(&XLlFifoInstance) != 0) {
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xil_printf("\n ERROR : RDFO is not becoming Empty : 0x%x \t"
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"Expected : 0x0 \n\n\r",
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XLlFifo_iRxOccupancy(&XLlFifoInstance));
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return XST_FAILURE;
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}
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if(XLlFifo_iRxGetLen(&XLlFifoInstance) != 0) {
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xil_printf("\n ERROR : RLR is not becoming Empty : 0x%x \t"
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"Expected : 0x0 \n\n\r",
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XLlFifo_iRxGetLen(&XLlFifoInstance));
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return XST_FAILURE;
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}
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return XST_SUCCESS;
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}
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#ifdef XPAR_UARTNS550_0_BASEADDR
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/*****************************************************************************/
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/*
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*
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* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
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*
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* @param None
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*
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* @return None
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*
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* @note None.
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*
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******************************************************************************/
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static void Uart550_Setup(void)
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{
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XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
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XPAR_XUARTNS550_CLOCK_HZ, 9600);
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XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
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XUN_LCR_8_DATA_BITS);
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}
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#endif
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