ee1d5c6b44
Added Modification history to xnandps.h file Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
447 lines
18 KiB
C
Executable file
447 lines
18 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xnandps.h
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*
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* This file implements a driver for the NAND flash controller.
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*
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* <b>Driver Initialization</b>
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*
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* The function call XNandPs_CfgInitialize() should be called by the application
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* before any other function in the driver. The initialization function takes
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* device specific data (like device id, instance id, and base address) and
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* initializes the XNandPs instance with the device specific data.
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*
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* <b>Device Geometry</b>
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*
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* NAND flash device is memory device and it is segmented into areas called
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* Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device
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* can have multiple LUN. LUN is sequential raw of multiple blocks of the same
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* size. A block is the smallest erasable unit of data within the Flash array of
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* a LUN. The size of each block is based on a power of 2. There is no
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* restriction on the number of blocks within the LUN. A block contains a number
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* of pages. A page is the smallest addressable unit for read and program
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* operations. The arrangement of LUN, blocks, and pages is referred to by this
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* module as the part's geometry.
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*
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* The cells within the part can be programmed from a logic 1 to a logic 0
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* and not the other way around. To change a cell back to a logic 1, the
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* entire block containing that cell must be erased. When a block is erased
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* all bytes contain the value 0xFF. The number of times a block can be
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* erased is finite. Eventually the block will wear out and will no longer
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* be capable of erasure. As of this writing, the typical flash block can
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* be erased 100,000 or more times.
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*
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* The jobs done by this driver typically are:
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* - 8/16 bit operational mode
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* - Read, Write, and Erase operation
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* - Read, Write cache operation
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* - Read, Write Spare area operation
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* - HW Error Check and Correction (ECC)
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*
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* <b>Write Operation</b>
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*
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* The write call can be used to write a minimum of one byte and a maximum
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* entire flash. If the address offset specified to write is out of flash or if
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* the number of bytes specified from the offset exceed flash boundaries
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* an error is reported back to the user. The write is blocking in nature in that
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* the control is returned back to user only after the write operation is
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* completed successfully or an error is reported.
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*
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* <b>Read Operation</b>
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*
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* The read call can be used to read a minimum of one byte and maximum of
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* entire flash. If the address offset specified to read is out of flash or if
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* the number of bytes specified from the offset exceed flash boundaries
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* an error is reported back to the user. The read is blocking in nature in that
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* the control is returned back to user only after the read operation is
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* completed successfully or an error is reported.
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*
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* <b>Erase Operation</b>
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*
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* The erase operations are provided to erase a Block in the Flash memory. The
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* erase call is blocking in nature in that the control is returned back to user
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* only after the erase operation is completed successfully or an error is
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* reported.
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*
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* <b>Page Cache Write Operation</b>
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*
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* The page cache write call is same as write call except that it uses cache
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* commands to write. This enhances the performance. This operation can't be
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* performed on OnDie ECC with internal ECC enabled. There is no way to disable
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* internal ECC for OnDie ECC flash parts in current driver. This operation
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* is tested with Spansion S34ML04G100TFI00 flash. We have to use this operation
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* only on the flash parts which supports program page cache command.
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*
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* <b>Page Cache Read Operation</b>
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*
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* The page cache read call is same as read call except that it uses cache
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* commands to read. This enhances the performance.
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* The read cache random command is used since the HW ECC block doesn't
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* support commands without address for starting ECC.
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* This operation can't be performed on OnDie ECC with internal ECC enabled.
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* There is no way to disable internal ECC for OnDie ECC flash parts in current
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* driver. This operation is tested with Spansion S34ML04G100TFI00 flash.
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* We have to use this operation only on the flash parts which supports
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* read page cache command (random).
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*
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* <b>Write Spare Bytes Operation</b>
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*
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* This call writes to user specified buffer into spare bytes of a page.
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*
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* <b>Read Spare Bytes Operation</b>
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*
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* This call reads spare bytes of a page into user specified buffer.
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*
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* @note
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*
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* This driver is intended to be RTOS and processor independent. It works with
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* physical addresses only. Any needs for dynamic memory management, threads,
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* mutual exclusion, virtual memory, cache control, or HW write protection
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* management must be satisfied by the layer above this driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- ---------- -----------------------------------------------
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* 1.00a nm 12/10/2010 First release
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* nm 29/09/2011 Added support for On-Die ECC NAND and Clean NAND
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* flash parts.
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* Added user spare buffer pointer to read/write
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* API's. Added new API's for reading and writing
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* spare buffer area.
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* Changes nand_cycles with ONFI timing mode 0.
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* Modified ONFI parameter page reading to read 3
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* mandatory pages.
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* 1.01a nm 28/02/2012 Added tcl file to generate xparameters.h.
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* Added support for 8Gb On-Die ECC NAND flash
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* parts (CR 648463).
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* Fixed 16-bit issue with ONFI commands like
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* read, write and read status command.
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* 1.02a nm 20/09/2012 Removed setting of set_cycles and set_opmode
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* register values as it is now done in FSBL using
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* the PCW generated files. CR#678949.
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* 1.03a nm 10/22/2012 Fixed CR# 683787,673348.
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* 1.04a nm 04/15/2013 Fixed CR# 704401. Removed warnings when compiled
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* with -Wall and -Wextra option in bsp.
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* 04/25/2013 Implemented PR# 699544. Added page cache read
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* and program support. Added API's XNandPs_ReadCache
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* and XNandPs_WriteCache for page cache support.
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* Added XNandPs_Features structure to XNandPs instance
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* which contains features handled by driver.
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* Added function prototypes for Page cache read/write
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* and spare byte read/write API's.
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* 2.0 adk 12/10/13 Updated as per the New Tcl API's
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* 2.1 kpc 07/24/13 Fixed CR#808770. Update command register twice only
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* if flash device requires >= four address cycles.
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* </pre>
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*
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******************************************************************************/
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#ifndef XNANDPS_H /* prevent circular inclusions */
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#define XNANDPS_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include <string.h> /* For memcpy, memset */
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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#include "xstatus.h"
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#include "xnandps_hw.h"
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/************************** Constant Definitions *****************************/
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#define XNANDPS_MAX_TARGETS 1 /**< Max number of targets
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supported */
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#define XNANDPS_MAX_BLOCKS 32768 /**< Max number of Blocks */
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#define XNANDPS_MAX_PAGE_SIZE 16384 /**< Max page size of NAND
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flash */
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#define XNANDPS_MAX_SPARE_SIZE 512 /**< Max spare bytes of a NAND
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flash page */
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#define XNANDPS_ECC_BLOCK_SIZE 512 /**< ECC block size */
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#define XNANDPS_ECC_BYTES 3 /**< ECC bytes per ECC block */
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#define XNANDPS_PAGE_SIZE_512 512 /**< Page size 512 */
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#define XNANDPS_PAGE_SIZE_1024 1024 /**< Page size 1024 */
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#define XNANDPS_PAGE_SIZE_2048 2048 /**< Page size 2048 */
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#define XNANDPS_PAGE_SIZE_4096 4096 /**< Page size 4096 */
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#define XNANDPS_PAGE_SIZE_8192 8192 /**< Page size 8192 */
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#define XNANDPS_SPARE_SIZE_8 8 /**< Spare bytes size 8 */
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#define XNANDPS_SPARE_SIZE_16 16 /**< Spare bytes size 16 */
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#define XNANDPS_SPARE_SIZE_32 32 /**< Spare bytes size 32 */
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#define XNANDPS_SPARE_SIZE_64 64 /**< Spare bytes size 64 */
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#define XNANDPS_SPARE_SIZE_128 128 /**< Spare bytes size 128 */
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#define XNANDPS_SPARE_SIZE_256 256 /**< Spare bytes size 256 */
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#define XNANDPS_FLASH_WIDTH_8 8 /**< NAND Flash width 8-bit */
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#define XNANDPS_FLASH_WIDTH_16 16 /**< NAND Flash width 16-bit */
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/* Macros used for framing SMC AXI command phase and Data phase address */
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#define XNANDPS_END_CMD_NONE 0 /**< No End command */
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#define XNANDPS_END_CMD_INVALID 0 /**< End command invalid */
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#define XNANDPS_CMD_PHASE 1 /**< End command in command
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phase */
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#define XNANDPS_DATA_PHASE 2 /**< End command in data
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phase */
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#define XNANDPS_PAGE_NOT_VALID -1 /**< Page is not valid in
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command phase */
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#define XNANDPS_COLUMN_NOT_VALID -1 /**< Column is not valid in
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command phase */
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#define XNANDPS_AXI_DATA_WIDTH 4 /**< AXI Data width for last
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transaction while reading
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and writing */
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/* Bit shift for AXI Command/Data phase address calculation */
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#define XNANDPS_START_CMD_SHIFT 3 /**< Start command shift */
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#define XNANDPS_END_CMD_SHIFT 11 /**< End command shift */
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#define XNANDPS_END_CMD_VALID_SHIFT 20 /**< End command valid shift */
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#define XNANDPS_ADDR_CYCLES_SHIFT 21 /**< Address cycles shift */
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#define XNANDPS_CHIP_ADDR_SHIFT 24 /**< Chip address shift */
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#define XNANDPS_ECC_LAST_SHIFT 10 /**< Ecc last shift */
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#define XNANDPS_CLEAR_CS_SHIFT 21 /**< clear chip select shift */
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#define XNANDPS_COMMAND_PHASE_MASK 0x00000000 /**< Command
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phase mask */
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#define XNANDPS_DATA_PHASE_MASK 0x00080000 /**< Data phase mask */
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/* Macros used for correcting ECC errors */
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#define XNANDPS_ECC_CORRECT_BYTE_MASK 0x1FF /**< ECC error correction byte
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position mask, bits[11:3] of
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error code */
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#define XNANDPS_ECC_CORRECT_BIT_MASK 0x7 /**< ECC error correction bit
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position mask, bits[0:2] of
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error code */
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/* Flash memory controller operating parameters */
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#define XNANDPS_CLR_CONFIG \
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((XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK) | \
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(XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK) | \
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(XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK))
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/**< Interrupt settings */
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#define XNANDPS_ECC_MEMCFG \
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((0x1 << XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT) | \
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(0x1 << XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT) | \
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(0x0 << XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT))
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/**< ECC memory configuration settings */
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#define XNANDPS_ECC_CMD1 \
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((0x80 << XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT) | \
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(0x00 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT) | \
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(0x30 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT) | \
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(0x1 << XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT))
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/**< ECC command 1 settings */
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#define XNANDPS_ECC_CMD2 \
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((0x85 << XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT) | \
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(0x05 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT) | \
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(0xE0 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT) | \
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(0x1 << XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT))
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/**< ECC command 2 settings */
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#define XNANDPS_CLR_CS (0x1 << XNANDPS_CLEAR_CS_SHIFT)
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/**< set Clear chip select */
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#define XNANDPS_ECC_LAST (0x1 << XNANDPS_ECC_LAST_SHIFT)
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/**< set Ecc last */
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/**************************** Type Definitions *******************************/
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/*
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* This enum contains ECC Mode
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*/
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typedef enum {
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XNANDPS_ECC_NONE = 0, /**< No ECC */
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XNANDPS_ECC_SW, /**< Software ECC */
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XNANDPS_ECC_HW, /**< Hardware controller ECC */
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XNANDPS_ECC_ONDIE /**< On-Die ECC */
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} XNandPs_EccMode;
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/**
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* This typedef contains configuration information for the flash device.
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*/
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typedef struct {
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u16 DeviceId; /**< Instance ID of device */
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u32 SmcBase; /**< SMC Base address */
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u32 FlashBase; /**< NAND base address */
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u32 FlashWidth; /**< Flash width */
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} XNandPs_Config;
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/**
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* Flash geometry
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*/
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typedef struct {
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u32 BytesPerPage; /**< Bytes per page */
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u16 SpareBytesPerPage; /**< Size of spare area in bytes */
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u32 PagesPerBlock; /**< Pages per block */
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u32 BlocksPerLun; /**< Bocks per LUN */
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u8 NumLun; /**< Total number of LUN */
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u8 FlashWidth; /**< Data width of flash device */
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u64 NumPages; /**< Total number of pages in device */
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u64 NumBlocks; /**< Total number of blocks in device */
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u64 BlockSize; /**< Size of a block in bytes */
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u64 DeviceSize; /**< Total device size in bytes */
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u8 RowAddrCycles; /**< Row address cycles */
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u8 ColAddrCycles; /**< Column address cycles */
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} XNandPs_Geometry;
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/**
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* ONFI Features and Optional commands supported
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* See parameter page byte 6-7 and 8-9
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*/
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typedef struct {
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int ProgramCache;
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int ReadCache;
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} XNandPs_Features;
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/**
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* Bad block table descriptor
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*/
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typedef struct {
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u32 PageOffset; /**< Page offset where BBT resides */
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u32 SigOffset; /**< Signature offset in Spare area */
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u32 VerOffset; /**< Offset of BBT version */
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u32 SigLength; /**< Length of the signature */
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u32 MaxBlocks; /**< Max blocks to search for BBT */
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char Signature[4]; /**< BBT signature */
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u8 Version; /**< BBT version */
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u32 Valid; /**< BBT descriptor is valid or not */
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} XNandPs_BbtDesc;
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/**
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* Bad block pattern
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*/
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typedef struct {
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u32 Options; /**< Options to search the bad block pattern */
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u32 Offset; /**< Offset to search for specified pattern */
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u32 Length; /**< Number of bytes to check the pattern */
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u8 Pattern[2]; /**< Pattern format to search for */
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} XNandPs_BadBlockPattern;
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/**
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* ECC configuration structure.
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* Contains information related to ECC.
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*/
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typedef struct {
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u32 NumSteps; /**< Number of ECC steps for the flash page */
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u32 BlockSize; /**< ECC block size */
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u32 BytesPerBlock; /**< Number of ECC bytes for a block */
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u32 TotalBytes; /**< Total number of ECC bytes for Page */
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u32 EccPos[XNANDPS_MAX_SPARE_SIZE];
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/**< ECC position in the spare area */
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} XNandPs_EccConfig;
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/**
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* The XNandPs driver instance data. The user is required to allocate a
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* variable of this type for every flash device in the system. A pointer to a
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* variable of this type is then passed to the driver API functions.
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*/
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typedef struct XNandPsTag {
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u32 IsReady; /**< Device is initialized and ready */
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XNandPs_Config Config; /**< XNandPs_Config of current
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device */
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XNandPs_Geometry Geometry; /**< Part geometry */
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XNandPs_Features Features; /**< Features and Optional commands */
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u32 CommandPhaseAddr; /**< NAND command phase address */
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u32 DataPhaseAddr; /**< NAND Data phase address */
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XNandPs_EccConfig EccConfig; /**< ECC configuration parameters */
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/* Bad block table definitions */
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XNandPs_BbtDesc BbtDesc; /**< Bad block table descriptor */
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XNandPs_BbtDesc BbtMirrorDesc; /**< Mirror BBT descriptor */
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XNandPs_BadBlockPattern BbPattern; /**< Bad block pattern to
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search */
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u8 Bbt[XNANDPS_MAX_BLOCKS >> 2]; /**< Bad block table array */
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u8 DataBuf[XNANDPS_MAX_PAGE_SIZE + XNANDPS_MAX_SPARE_SIZE];
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/**< Data buffer for partial read/writes */
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u8 *SpareBufPtr; /**< Pointer to store spare buffer */
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u8 EccCalc[XNANDPS_MAX_SPARE_SIZE]; /**< Buffer for calculated
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ECC */
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u8 EccCode[XNANDPS_MAX_SPARE_SIZE]; /**< Buffer for stored ECC */
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XNandPs_EccMode EccMode; /**< ECC Mode */
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int (*ReadPage) (struct XNandPsTag *InstancePtr, u8 *DstPtr);
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/**< Read Page routine */
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int (*WritePage) (struct XNandPsTag *InstancePtr, u8 *SrcPtr);
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/**< Write Page routine */
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} XNandPs;
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/**
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* NAND Command format structures
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*/
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typedef struct {
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int StartCmd; /**< Start command */
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int EndCmd; /**< End command */
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u8 AddrCycles; /**< Number of address cycles */
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u8 EndCmdValid; /**< End command valid */
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} XNandPs_CommandFormat;
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/***************** Macros (Inline Functions) Definitions *********************/
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/**
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* OneHot is used to check if one and only one bit is set.
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* This Macro returns 1 if the value passed is OneHot.
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*/
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#define OneHot(Value) (!((Value) & (Value - 1)))
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/************************** Function Prototypes ******************************/
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/*
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* Functions in xnandps_sinit.c
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*/
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XNandPs_Config *XNandPs_LookupConfig(u16 DeviceId);
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/*
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* Functions in xnandps.c
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*/
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/*
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* Initialization, read, write and erase functions.
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*/
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int XNandPs_CfgInitialize(XNandPs *InstancePtr, XNandPs_Config *ConfigPtr,
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u32 SmcBaseAddr, u32 FlashBaseAddr);
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int XNandPs_Read(XNandPs *InstancePtr, u64 Offset, u32 Bytes, void *DestPtr,
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u8 *UserSparePtr);
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|
int XNandPs_ReadCache(XNandPs *InstancePtr, u64 Offset, u32 Bytes,
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|
void *SrcPtr, u8 *UserSparePtr);
|
|
int XNandPs_Write(XNandPs *InstancePtr, u64 Offset, u32 Bytes, void *SrcPtr,
|
|
u8 *UserSparePtr);
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|
int XNandPs_WriteCache(XNandPs *InstancePtr, u64 Offset, u32 Length,
|
|
void *SrcPtr, u8 *UserSparePtr);
|
|
int XNandPs_ReadSpareBytes(XNandPs *InstancePtr, u32 Page, u8 *Buf);
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|
int XNandPs_WriteSpareBytes(XNandPs *InstancePtr, u32 Page, u8 *Buf);
|
|
int XNandPs_EraseBlock(XNandPs *InstancePtr, u32 BlockNum);
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|
#ifdef __cplusplus
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|
}
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|
#endif
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|
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#endif /* end of protection macro */
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