2dee01e56d
This patch updates the standalone files copyright information with the latest content. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
160 lines
4.9 KiB
C
160 lines
4.9 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file uart.c
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*
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* This file contains APIs for configuring the UART.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 5.00 pkp 02/20/14 First release
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* </pre>
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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#include "xil_types.h"
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#include "xparameters.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/* Register offsets */
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#define UART_CR_OFFSET 0x00000000U
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#define UART_MR_OFFSET 0x00000004U
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#define UART_BAUDGEN_OFFSET 0x00000018U
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#define UART_BAUDDIV_OFFSET 0x00000034U
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#define MAX_BAUD_ERROR_RATE 0x00000003U /* max % error allowed */
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#define UART_BAUDRATE 115200U
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#define CSU_VERSION_REG 0xFFCA0044U
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void Init_Uart(void);
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void Init_Uart(void)
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{
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#ifdef STDOUT_BASEADDRESS
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u8 IterBAUDDIV; /* Iterator for available baud divisor values */
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u32 BRGR_Value; /* Calculated value for baud rate generator */
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u32 CalcBaudRate; /* Calculated baud rate */
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u32 BaudError; /* Diff between calculated and requested baud rate */
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u32 Best_BRGR = 0U; /* Best value for baud rate generator */
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u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
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u32 Best_Error = 0xFFFFFFFFU;
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u32 PercentError;
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u32 InputClk;
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u32 BaudRate = UART_BAUDRATE;
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#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
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InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
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#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
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InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
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#else
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/* STDIO is not set or axi_uart is being used for STDIO */
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return;
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#endif
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InputClk = 25000000U;
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/*
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* Determine the Baud divider. It can be 4to 254.
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* Loop through all possible combinations
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*/
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for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
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/*
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* Calculate the value for BRGR register
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*/
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BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 0x00000001U));
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/*
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* Calculate the baud rate from the BRGR value
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*/
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CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 0x00000001U));
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/*
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* Avoid unsigned integer underflow
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*/
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if (BaudRate > CalcBaudRate) {
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BaudError = BaudRate - CalcBaudRate;
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} else {
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BaudError = CalcBaudRate - BaudRate;
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}
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/*
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* Find the calculated baud rate closest to requested baud rate.
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*/
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if (Best_Error > BaudError) {
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Best_BRGR = BRGR_Value;
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Best_BAUDDIV = IterBAUDDIV;
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Best_Error = BaudError;
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}
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}
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/*
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* Make sure the best error is not too large.
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*/
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PercentError = (Best_Error * 100U) / BaudRate;
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if (MAX_BAUD_ERROR_RATE < PercentError) {
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return;
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}
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/* set CD and BDIV */
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
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/*
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* Veloce specific code
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*/
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if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 0x00000002U);
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Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 0x00000004U);
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}
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/*
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* 8 data, 1 stop, 0 parity bits
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* sel_clk=uart_clk=APB clock
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*/
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Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
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/* enable Tx/Rx and reset Tx/Rx data path */
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Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
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return;
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#endif
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}
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