8296dcd0f1
This patch modifies the code according to MISRA-C 2012 and added support for ZynqMP. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
309 lines
11 KiB
C
309 lines
11 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xspips_hw.h
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*
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* This header file contains the identifiers and basic driver functions (or
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* macros) that can be used to access the device. Other driver functions
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* are defined in xspips.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- -----------------------------------------------
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* 1.00 drg/jz 01/25/10 First release
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* 1.02a sg 05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
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* for CR 658289
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* 1.04a sg 01/30/13 Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
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* to XSPIPS_CR_RESET_STATE. Created
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* XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
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* write-to-clear. Added shift and mask macros for d_nss
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* parameter. Added Rx Watermark mask.
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* 1.06a hk 08/22/13 Added prototypes of reset API and related constant
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* definitions.
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XSPIPS_HW_H /* prevent circular inclusions */
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#define XSPIPS_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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*
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* Register offsets from the base address of an SPI device.
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* @{
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*/
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#define XSPIPS_CR_OFFSET 0x00U /**< Configuration */
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#define XSPIPS_SR_OFFSET 0x04U /**< Interrupt Status */
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#define XSPIPS_IER_OFFSET 0x08U /**< Interrupt Enable */
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#define XSPIPS_IDR_OFFSET 0x0CU /**< Interrupt Disable */
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#define XSPIPS_IMR_OFFSET 0x10U /**< Interrupt Enabled Mask */
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#define XSPIPS_ER_OFFSET 0x14U /**< Enable/Disable Register */
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#define XSPIPS_DR_OFFSET 0x18U /**< Delay Register */
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#define XSPIPS_TXD_OFFSET 0x1CU /**< Data Transmit Register */
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#define XSPIPS_RXD_OFFSET 0x20U /**< Data Receive Register */
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#define XSPIPS_SICR_OFFSET 0x24U /**< Slave Idle Count */
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#define XSPIPS_TXWR_OFFSET 0x28U /**< Transmit FIFO Watermark */
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#define XSPIPS_RXWR_OFFSET 0x2CU /**< Receive FIFO Watermark */
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/* @} */
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/** @name Configuration Register
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*
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* This register contains various control bits that
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* affects the operation of an SPI device. Read/Write.
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* @{
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*/
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#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U /**< Modefail Generation
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Enable */
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#define XSPIPS_CR_MANSTRT_MASK 0x00010000U /**< Manual Transmission Start */
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#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000U /**< Manual Transmission Start
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Enable */
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#define XSPIPS_CR_SSFORCE_MASK 0x00004000U /**< Force Slave Select */
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#define XSPIPS_CR_SSCTRL_MASK 0x00003C00U /**< Slave Select Decode */
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#define XSPIPS_CR_SSCTRL_SHIFT 10U /**< Slave Select Decode shift */
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#define XSPIPS_CR_SSCTRL_MAXIMUM 0xFU /**< Slave Select maximum value */
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#define XSPIPS_CR_SSDECEN_MASK 0x00000200U /**< Slave Select Decode Enable */
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#define XSPIPS_CR_PRESC_MASK 0x00000038U /**< Prescaler Setting */
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#define XSPIPS_CR_PRESC_SHIFT 3U /**< Prescaler shift */
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#define XSPIPS_CR_PRESC_MAXIMUM 0x07U /**< Prescaler maximum value */
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#define XSPIPS_CR_CPHA_MASK 0x00000004U /**< Phase Configuration */
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#define XSPIPS_CR_CPOL_MASK 0x00000002U /**< Polarity Configuration */
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#define XSPIPS_CR_MSTREN_MASK 0x00000001U /**< Master Mode Enable */
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#define XSPIPS_CR_RESET_STATE 0x00020000U /**< Mode Fail Generation Enable */
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/* @} */
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/** @name SPI Interrupt Registers
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*
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* <b>SPI Status Register</b>
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*
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* This register holds the interrupt status flags for an SPI device. Some
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* of the flags are level triggered, which means that they are set as long
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* as the interrupt condition exists. Other flags are edge triggered,
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* which means they are set once the interrupt condition occurs and remain
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* set until they are cleared by software. The interrupts are cleared by
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* writing a '1' to the interrupt bit position in the Status Register.
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* Read/Write.
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*
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* <b>SPI Interrupt Enable Register</b>
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*
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* This register is used to enable chosen interrupts for an SPI device.
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* Writing a '1' to a bit in this register sets the corresponding bit in the
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* SPI Interrupt Mask register. Write only.
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*
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* <b>SPI Interrupt Disable Register </b>
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*
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* This register is used to disable chosen interrupts for an SPI device.
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* Writing a '1' to a bit in this register clears the corresponding bit in the
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* SPI Interrupt Mask register. Write only.
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*
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* <b>SPI Interrupt Mask Register</b>
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*
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* This register shows the enabled/disabled interrupts of an SPI device.
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* Read only.
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*
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* All four registers have the same bit definitions. They are only defined once
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* for each of the Interrupt Enable Register, Interrupt Disable Register,
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* Interrupt Mask Register, and Channel Interrupt Status Register
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* @{
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*/
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#define XSPIPS_IXR_TXUF_MASK 0x00000040U /**< Tx FIFO Underflow */
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#define XSPIPS_IXR_RXFULL_MASK 0x00000020U /**< Rx FIFO Full */
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#define XSPIPS_IXR_RXNEMPTY_MASK 0x00000010U /**< Rx FIFO Not Empty */
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#define XSPIPS_IXR_TXFULL_MASK 0x00000008U /**< Tx FIFO Full */
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#define XSPIPS_IXR_TXOW_MASK 0x00000004U /**< Tx FIFO Overwater */
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#define XSPIPS_IXR_MODF_MASK 0x00000002U /**< Mode Fault */
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#define XSPIPS_IXR_RXOVR_MASK 0x00000001U /**< Rx FIFO Overrun */
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#define XSPIPS_IXR_DFLT_MASK 0x00000027U /**< Default interrupts
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mask */
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#define XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043U /**< Interrupts which
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need write to clear */
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#define XSPIPS_ISR_RESET_STATE 0x04U /**< Default to tx/rx
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* reg empty */
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#define XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043U /**< Disable all
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* interrupts */
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/* @} */
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/** @name Enable Register
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*
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* This register is used to enable or disable an SPI device.
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* Read/Write
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* @{
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*/
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#define XSPIPS_ER_ENABLE_MASK 0x00000001U /**< SPI Enable Bit Mask */
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/* @} */
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/** @name Delay Register
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*
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* This register is used to program timing delays in
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* slave mode. Read/Write
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* @{
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*/
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#define XSPIPS_DR_NSS_MASK 0xFF000000U /**< Delay for slave select
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* de-assertion between
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* word transfers mask */
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#define XSPIPS_DR_NSS_SHIFT 24U /**< Delay for slave select
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* de-assertion between
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* word transfers shift */
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#define XSPIPS_DR_BTWN_MASK 0x00FF0000U /**< Delay Between Transfers mask */
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#define XSPIPS_DR_BTWN_SHIFT 16U /**< Delay Between Transfers shift */
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#define XSPIPS_DR_AFTER_MASK 0x0000FF00U /**< Delay After Transfers mask */
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#define XSPIPS_DR_AFTER_SHIFT 8U /**< Delay After Transfers shift */
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#define XSPIPS_DR_INIT_MASK 0x000000FFU /**< Delay Initially mask */
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/* @} */
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/** @name Slave Idle Count Registers
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*
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* This register defines the number of pclk cycles the slave waits for a the
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* SPI clock to become stable in quiescent state before it can detect the start
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* of the next transfer in CPHA = 1 mode.
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* Read/Write
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*
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* @{
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*/
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#define XSPIPS_SICR_MASK 0x000000FFU /**< Slave Idle Count Mask */
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/* @} */
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/** @name Transmit FIFO Watermark Register
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*
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* This register defines the watermark setting for the Transmit FIFO. The
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* transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values
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* are 1 to 128.
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*
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* @{
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*/
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#define XSPIPS_TXWR_MASK 0x0000007FU /**< Transmit Watermark Mask */
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#define XSPIPS_TXWR_RESET_VALUE 0x00000001U /**< Transmit Watermark
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* register reset value */
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/* @} */
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/** @name Receive FIFO Watermark Register
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*
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* This register defines the watermark setting for the Receive FIFO. The
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* receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values
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* are 1 to 128.
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*
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* @{
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*/
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#define XSPIPS_RXWR_MASK 0x0000007FU /**< Receive Watermark Mask */
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#define XSPIPS_RXWR_RESET_VALUE 0x00000001U /**< Receive Watermark
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* register reset value */
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/* @} */
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/** @name FIFO Depth
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*
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* This macro provides the depth of transmit FIFO and receive FIFO.
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*
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* @{
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*/
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#define XSPIPS_FIFO_DEPTH 128U /**< FIFO depth of Tx and Rx */
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/* @} */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XSpiPs_In32 Xil_In32
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#define XSpiPs_Out32 Xil_Out32
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/****************************************************************************/
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/**
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* Read a register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to the target register.
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*
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* @return The value read from the register.
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*
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* @note C-Style signature:
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* u32 XSpiPs_ReadReg(u32 BaseAddress. int RegOffset)
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*
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******************************************************************************/
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#define XSpiPs_ReadReg(BaseAddress, RegOffset) \
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XSpiPs_In32((BaseAddress) + (RegOffset))
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/***************************************************************************/
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/**
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* Write to a register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to target register.
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* @param RegisterValue is the value to be written to the register.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XSpiPs_WriteReg(u32 BaseAddress, int RegOffset,
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* u32 RegisterValue)
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*
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******************************************************************************/
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#define XSpiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
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XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
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/************************** Function Prototypes ******************************/
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void XSpiPs_ResetHw(u32 BaseAddress);
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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