Sarat Chand Savitala 71d7769303 sw_apps:zynqmp_fsbl: Change of invalid load address value for PL bitstream ... When load address is not mentioned for PL bitstream, bootgen now makes this as 0xFFFFFFFF to indicate it is invalid. Hence, FSBL uses default address to load bitstream when load address from bootgen is 0xFFFFFFFF. Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com> Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>		2015-08-17 09:09:03 +05:30
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bsp	bsp: a53: modified translation table in a53 32bit bsp	2015-08-10 14:26:48 +05:30
sw_apps	sw_apps:zynqmp_fsbl: Change of invalid load address value for PL bitstream	2015-08-17 09:09:03 +05:30
sw_services	xilisf: Modified SPIPS examples to support on ZynqMP.	2015-08-10 17:14:36 +05:30