2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
239 lines
9.1 KiB
C
Executable file
239 lines
9.1 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xaxicdma_hw.h
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*
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* Hardware definition file. It defines the register interface and Buffer
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* Descriptor (BD) definitions.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 04/08/10 First release
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* 2.02a srt 01/18/13 Added support for Key Hole feature (CR: 687217).
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* </pre>
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*
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*****************************************************************************/
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#ifndef XAXICDMA_HW_H_ /* prevent circular inclusions */
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#define XAXICDMA_HW_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "xil_types.h"
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#include "xil_io.h"
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#include "xparameters.h"
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/************************** Constant Definitions *****************************/
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/** @name Buffer Descriptor Alignment
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* @{
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*/
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#define XAXICDMA_BD_MINIMUM_ALIGNMENT 0x40 /**< Minimum byte alignment
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requirement for descriptors to
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satisfy both hardware/software
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needs */
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/*@}*/
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/** @name Maximum transfer length
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* This is determined by hardware
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* @{
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*/
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#define XAXICDMA_MAX_TRANSFER_LEN 0x7FFFFF /**< Max length hw supports */
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/*@}*/
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/** @name Register offset definitions
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* Register accesses are 32-bit.
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* @{
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*/
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#define XAXICDMA_CR_OFFSET 0x00000000 /**< Control register */
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#define XAXICDMA_SR_OFFSET 0x00000004 /**< Status register */
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#define XAXICDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */
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#define XAXICDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */
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#define XAXICDMA_SRCADDR_OFFSET 0x00000018 /**< Source address register */
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#define XAXICDMA_DSTADDR_OFFSET 0x00000020 /**< Destination address register */
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#define XAXICDMA_BTT_OFFSET 0x00000028 /**< Bytes to transfer */
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/*@}*/
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/** @name Bitmasks of XAXICDMA_CR_OFFSET register
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* @{
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*/
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#define XAXICDMA_CR_RESET_MASK 0x00000004 /**< Reset DMA engine */
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#define XAXICDMA_CR_SGMODE_MASK 0x00000008 /**< Scatter gather mode */
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#define XAXICDMA_CR_KHOLE_RD_MASK 0x00000010 /**< Keyhole Read */
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#define XAXICDMA_CR_KHOLE_WR_MASK 0x00000020 /**< Keyhole Write */
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/*@}*/
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/** @name Bitmasks of XAXICDMA_SR_OFFSET register
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* This register reports status of a DMA channel, including
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* idle state, errors, and interrupts
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* @{
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*/
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#define XAXICDMA_SR_IDLE_MASK 0x00000002 /**< DMA channel idle */
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#define XAXICDMA_SR_SGINCLD_MASK 0x00000008 /**< Hybrid build */
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#define XAXICDMA_SR_ERR_INTERNAL_MASK 0x00000010 /**< Datamover internal err */
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#define XAXICDMA_SR_ERR_SLAVE_MASK 0x00000020 /**< Datamover slave err */
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#define XAXICDMA_SR_ERR_DECODE_MASK 0x00000040 /**< Datamover decode err */
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#define XAXICDMA_SR_ERR_SG_INT_MASK 0x00000100 /**< SG internal err */
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#define XAXICDMA_SR_ERR_SG_SLV_MASK 0x00000200 /**< SG slave err */
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#define XAXICDMA_SR_ERR_SG_DEC_MASK 0x00000400 /**< SG decode err */
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#define XAXICDMA_SR_ERR_ALL_MASK 0x00000770 /**< All errors */
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/*@}*/
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/** @name Bitmask for interrupts
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* These masks are shared by XAXICDMA_CR_OFFSET register and
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* XAXICDMA_SR_OFFSET register
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* @{
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*/
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#define XAXICDMA_XR_IRQ_IOC_MASK 0x00001000 /**< Completion interrupt */
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#define XAXICDMA_XR_IRQ_DELAY_MASK 0x00002000 /**< Delay interrupt */
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#define XAXICDMA_XR_IRQ_ERROR_MASK 0x00004000 /**< Error interrupt */
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#define XAXICDMA_XR_IRQ_ALL_MASK 0x00007000 /**< All interrupts */
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#define XAXICDMA_XR_IRQ_SIMPLE_ALL_MASK 0x00005000 /**< All interrupts for
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simple only mode */
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/*@}*/
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/** @name Bitmask and shift for delay counter and coalescing counter
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* These masks are shared by XAXICDMA_CR_OFFSET register and
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* XAXICDMA_SR_OFFSET register
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* @{
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*/
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#define XAXICDMA_XR_DELAY_MASK 0xFF000000 /**< Delay timeout counter */
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#define XAXICDMA_XR_COALESCE_MASK 0x00FF0000 /**< Coalesce counter */
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#define XAXICDMA_DELAY_SHIFT 24
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#define XAXICDMA_COALESCE_SHIFT 16
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#define XAXICDMA_DELAY_MAX 0xFF /**< Maximum delay counter value */
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#define XAXICDMA_COALESCE_MAX 0xFF /**< Maximum coalescing counter value */
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/*@}*/
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/* Buffer Descriptor (BD) definitions
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*/
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/** @name Buffer Descriptor offsets
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* The first 8 words are used by hardware.
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* Cache operations are required for words used by hardware to enforce data
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* consistency.
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* All words after the 8th word are for software use only.
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* @{
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*/
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#define XAXICDMA_BD_NDESC_OFFSET 0x00 /**< Next descriptor pointer */
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#define XAXICDMA_BD_BUFSRC_OFFSET 0x08 /**< Buffer source address */
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#define XAXICDMA_BD_BUFDST_OFFSET 0x10 /**< Buffer destination address */
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#define XAXICDMA_BD_CTRL_LEN_OFFSET 0x18 /**< Control/buffer length */
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#define XAXICDMA_BD_STS_OFFSET 0x1C /**< Status */
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#define XAXICDMA_BD_PHYS_ADDR_OFFSET 0x20 /**< Physical address of the BD */
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#define XAXICDMA_BD_ISLITE_OFFSET 0x24 /**< Lite mode hardware build? */
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#define XAXICDMA_BD_HASDRE_OFFSET 0x28 /**< Support unaligned transfers? */
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#define XAXICDMA_BD_WORDLEN_OFFSET 0x2C /**< Word length in bytes */
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#define XAXICDMA_BD_MAX_LEN_OFFSET 0x30 /**< Word length in bytes */
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#define XAXICDMA_BD_START_CLEAR 8 /**< Offset to start clear */
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#define XAXICDMA_BD_TO_CLEAR 24 /**< BD specific bytes to be cleared */
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#define XAXICDMA_BD_NUM_WORDS 16 /**< Total number of words for one BD*/
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#define XAXICDMA_BD_HW_NUM_BYTES 32 /**< Number of bytes hw used */
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/*@}*/
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/** @name Bitmasks of XAXICDMA_BD_CTRL_OFFSET register
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* @{
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*/
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#define XAXICDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /**< Requested len */
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/*@}*/
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/** @name Bitmasks of XAXICDMA_BD_STS_OFFSET register
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* @{
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*/
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#define XAXICDMA_BD_STS_COMPLETE_MASK 0x80000000 /**< Completed */
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#define XAXICDMA_BD_STS_DEC_ERR_MASK 0x40000000 /**< Decode error */
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#define XAXICDMA_BD_STS_SLV_ERR_MASK 0x20000000 /**< Slave error */
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#define XAXICDMA_BD_STS_INT_ERR_MASK 0x10000000 /**< Internal err */
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#define XAXICDMA_BD_STS_ALL_ERR_MASK 0x70000000 /**< All errors */
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#define XAXICDMA_BD_STS_ALL_MASK 0xF0000000 /**< All status bits */
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/*@}*/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XAxiCdma_In32 Xil_In32
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#define XAxiCdma_Out32 Xil_Out32
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/*****************************************************************************/
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/**
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*
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* Read a given register.
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*
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* @param BaseAddress is the base virtual address of the device
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* @param RegOffset is the register offset to be read
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*
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* @return The 32-bit value of the register
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*
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* @note
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* C-style signature:
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* u32 XAxiCdma_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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******************************************************************************/
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#define XAxiCdma_ReadReg(BaseAddress, RegOffset) \
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XAxiCdma_In32((BaseAddress) + (RegOffset))
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/*****************************************************************************/
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/**
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*
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* Write to a given register.
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*
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* @param BaseAddress is the base virtual address of the device
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* @param RegOffset is the register offset to be written
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* @param Data is the 32-bit value to write to the register
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void XAxiCdma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
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*
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******************************************************************************/
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#define XAxiCdma_WriteReg(BaseAddress, RegOffset, Data) \
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XAxiCdma_Out32((BaseAddress) + (RegOffset), (Data))
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#ifdef __cplusplus
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}
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#endif
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#endif
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