2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
429 lines
13 KiB
C
Executable file
429 lines
13 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xtrafgen_polling_example.c
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*
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* This file demonstrates how to use the xtrafgen driver on the Xilinx AXI
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* Traffic Generator core. The AXI Traffic Generator IP is designed to
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* generate AXI4 traffic which can be used to stress different modules/
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* interconnect connected in the system. It has three internal RAMS: MASTER
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* RAM, COMMAND RAM, PARAMETER RAM. MASTER RAM is used to load/store data from
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* this memory for write/read transactions. And the commands to be issued are
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* loaded into COMMAND and PARAMETER RAMs.
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*
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* This example demonstrates by programming known data to Master RAM and
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* commands to Command and Param RAM. Initiating the master logic will take
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* the data from Master RAM (from a location) and generate data for slave
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* transactions which will be stored in Master RAM at a different location
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* specified by commands. The test passes when the master logic completes and
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* verifies for data to be same.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a srt 01/25/13 First release
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*
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* </pre>
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*
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* ***************************************************************************
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*/
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/***************************** Include Files *********************************/
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#include "xtrafgen.h"
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#include "xparameters.h"
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#include "xil_exception.h"
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#ifdef XPAR_UARTNS550_0_BASEADDR
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#include "xuartns550_l.h" /* to use uartns550 */
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#endif
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define TRAFGEN_DEV_ID XPAR_XTRAFGEN_0_DEVICE_ID
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#ifdef XPAR_V6DDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_V6DDR_0_S_AXI_BASEADDR
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#elif XPAR_S6DDR_0_S0_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_S6DDR_0_S0_AXI_BASEADDR
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#elif XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#define DDR_BASE_ADDR XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
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#elif XPAR_MIG_7SERIES_1_BASEADDR
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#define DDR_BASE_ADDR XPAR_MIG_7SERIES_1_BASEADDR
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#elif XPAR_MIG7SERIES_0_BASEADDR
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#define DDR_BASE_ADDR XPAR_MIG7SERIES_0_BASEADDR
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#endif
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#ifndef DDR_BASE_ADDR
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#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
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DEFAULT SET TO 0x01000000
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#define MEM_BASE_ADDR 0x01000000
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#else
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#define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000)
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#endif
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#define AXI_ADDRESS MEM_BASE_ADDR
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#define TEST_LENGTH 0x8
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#define MSTRRAM_INDEX (TEST_LENGTH) * 4
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#undef DEBUG
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/************************** Function Prototypes ******************************/
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int XTrafGenPollingExample(XTrafGen *InstancePtr, u16 DeviceId);
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void InitDefaultCommands(XTrafGen_Cmd *CmdPtr);
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#ifdef XPAR_UARTNS550_0_BASEADDR
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static void Uart550_Setup(void);
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#endif
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/************************** Variable Definitions *****************************/
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/*
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* Device instance definitions
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*/
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XTrafGen XTrafGenInstance;
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/*
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* Test Data to write into Master RAM
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*/
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u32 MasterRamData[TEST_LENGTH] = {0x00000000,
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0x11111111,
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0x22222222,
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0x33333333,
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0x44444444,
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0x55555555,
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0x66666666,
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0x77777777,
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};
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/*
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* Data read from Master RAM
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*/
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u32 VerifyRamData[TEST_LENGTH];
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/*****************************************************************************/
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/**
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*
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* Main function
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*
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* This function is the main entry of the traffic generator test.
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*
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* @param None
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*
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* @return - XST_SUCCESS if tests pass
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* - XST_FAILURE if fails.
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*
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* @note None.
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*
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******************************************************************************/
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int main()
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{
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int Status;
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xil_printf("Entering main\n\r");
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Status = XTrafGenPollingExample(&XTrafGenInstance, TRAFGEN_DEV_ID);
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if (Status != XST_SUCCESS) {
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xil_printf("Traffic Generator Polling Example Test Failed\n\r");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_FAILURE;
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}
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xil_printf("Traffic Generator Polling Example Test passed\n\r");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* This function demonstrates the usage Traffic Generator
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* It does the following:
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* - Set up the output terminal if UART16550 is in the hardware build
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* - Initialize the AXI Traffic Generator device
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* - Initialize Master RAM
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* - Initialize commands and add them to list
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* - Program internal command and parameter RAMs
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* - Start Master Logic
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* - Wait for the master logic to finish
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* - Check for errors
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* - Read Master RAM and verify data
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* - Return test status and exit
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*
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* @param InstancePtr is a pointer to the instance of the
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* XTrafGen component.
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* @param DeviceId is Device ID of the Axi Traffic Generator Device,
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*
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*
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* @param InstancePtr is a pointer to the instance of the
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* XTrafGen component.
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* @param DeviceId is Device ID of the Axi Traffic Generator Device,
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* typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
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* xparameters.h.
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*
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* @return -XST_SUCCESS to indicate success
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* -XST_FAILURE to indicate failure
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*
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******************************************************************************/
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int XTrafGenPollingExample(XTrafGen *InstancePtr, u16 DeviceId)
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{
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XTrafGen_Config *Config;
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XTrafGen_Cmd Cmd;
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XTrafGen_Cmd *CmdPtr = &Cmd;
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u32 MasterRamIndex = 0;
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u32 Done;
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u32 Error;
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int Status = XST_SUCCESS;
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int Index;
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/* Initial setup for Uart16550 */
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#ifdef XPAR_UARTNS550_0_BASEADDR
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Uart550_Setup();
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#endif
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/* Initialize the Device Configuration Interface driver */
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Config = XTrafGen_LookupConfig(DeviceId);
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if (!Config) {
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xil_printf("No config found for %d\r\n", DeviceId);
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return XST_FAILURE;
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}
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/*
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* This is where the virtual address would be used, this example
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* uses physical address.
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*/
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Status = XTrafGen_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
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if (Status != XST_SUCCESS) {
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xil_printf("Initialization failed\n\r");
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return Status;
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}
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/* Program Master RAM with Test Data */
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XTrafGen_AccessMasterRam(InstancePtr, MasterRamIndex,
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sizeof(MasterRamData), XTG_WRITE, MasterRamData);
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/* Initialize default command fields */
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InitDefaultCommands(CmdPtr);
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/* Add Valid Command for Write Region */
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CmdPtr->CRamCmd.Address = AXI_ADDRESS;
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CmdPtr->CRamCmd.MasterRamIndex = 0x0;
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CmdPtr->CRamCmd.Length = TEST_LENGTH - 1;
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CmdPtr->RdWrFlag = XTG_WRITE;
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CmdPtr->CRamCmd.ValidCmd = 1;
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CmdPtr->CRamCmd.MyDepend = 0;
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CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
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XTG_WRITE) + 1;
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Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
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if (Status != XST_SUCCESS) {
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xil_printf("AddCommand() failed\n\r");
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return Status;
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}
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/* Add Valid Command for Read Region */
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CmdPtr->CRamCmd.Address = AXI_ADDRESS;
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CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
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CmdPtr->CRamCmd.Length = 7;
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CmdPtr->CRamCmd.Size = 0x2;
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CmdPtr->RdWrFlag = XTG_READ;
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CmdPtr->CRamCmd.ValidCmd = 1;
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CmdPtr->CRamCmd.MyDepend = 0;
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/* Make this command dependent on Write logic command 1 */
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CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
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XTG_WRITE) + 1;
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Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
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if (Status != XST_SUCCESS) {
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xil_printf("AddCommand() failed\n\r");
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return Status;
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}
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/* Add second valid command to Write Region */
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CmdPtr->CRamCmd.Address = AXI_ADDRESS + MSTRRAM_INDEX;
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CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX;
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CmdPtr->CRamCmd.Length = 0;
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CmdPtr->RdWrFlag = XTG_WRITE;
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CmdPtr->CRamCmd.ValidCmd = 1;
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CmdPtr->CRamCmd.MyDepend = 0;
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/* Make this command dependent on Read logic command 1 */
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CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
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XTG_READ) + 1;
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Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
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if (Status != XST_SUCCESS) {
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xil_printf("AddCommand() failed\n\r");
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return Status;
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}
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/* Add invalid command at the end of Write Queue */
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CmdPtr->CRamCmd.Address = AXI_ADDRESS;
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CmdPtr->CRamCmd.MasterRamIndex = 0x0;
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CmdPtr->RdWrFlag = XTG_WRITE;
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CmdPtr->CRamCmd.Size = 0;
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CmdPtr->CRamCmd.ValidCmd = 0;
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CmdPtr->CRamCmd.MyDepend = 0;
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/* Make this command dependent on Read logic command 1 */
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CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
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XTG_READ) + 1;;
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Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
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if (Status != XST_SUCCESS) {
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xil_printf("AddCommand() failed\n\r");
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return Status;
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}
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/* Add invalid command at the end of Read Queue */
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CmdPtr->CRamCmd.MasterRamIndex = 0x0;
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CmdPtr->RdWrFlag = XTG_READ;
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CmdPtr->CRamCmd.Length = 0;
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CmdPtr->CRamCmd.Size = 0x0;
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CmdPtr->CRamCmd.ValidCmd = 0;
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/* Make this command dependent on Write logic command 2 */
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CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr,
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XTG_WRITE) + 1;
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Status = XTrafGen_AddCommand(InstancePtr, CmdPtr);
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if (Status != XST_SUCCESS) {
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xil_printf("AddCommand() failed\n\r");
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return Status;
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}
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/* Display Command list */
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#ifdef DEBUG
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XTrafGen_PrintCmds(InstancePtr);
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#endif
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/* Program all prepared commands */
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Status = XTrafGen_WriteCmdsToHw(InstancePtr);
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if (Status != XST_SUCCESS) {
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xil_printf("WriteCmdsToHw() failed\n\r");
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return Status;
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}
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/* Start Master Logic */
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XTrafGen_StartMasterLogic(InstancePtr);
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while (1) {
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Done = XTrafGen_IsMasterLogicDone(InstancePtr);
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if (Done) {
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break;
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}
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Error = XTrafGen_ReadErrors(InstancePtr);
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if (Error) {
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XTrafGen_ClearErrors(InstancePtr, Error);
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return XST_FAILURE;
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}
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}
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/* Read Master RAM */
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XTrafGen_AccessMasterRam(InstancePtr, MSTRRAM_INDEX,
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sizeof(MasterRamData), XTG_READ, VerifyRamData);
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/* Verify Data */
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for (Index = 0 ; Index < TEST_LENGTH - 1; Index++) {
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if (VerifyRamData[Index] != MasterRamData[Index]) {
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xil_printf("Data Mismatch\n\r");
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return XST_FAILURE;
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}
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}
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return XST_SUCCESS;
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}
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#ifdef XPAR_UARTNS550_0_BASEADDR
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/*****************************************************************************/
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/*
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*
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* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
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*
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* @param None
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*
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* @return None
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*
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* @note None.
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*
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******************************************************************************/
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static void Uart550_Setup(void)
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{
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XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
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XPAR_XUARTNS550_CLOCK_HZ, 9600);
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XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
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XUN_LCR_8_DATA_BITS);
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}
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#endif
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/*****************************************************************************/
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/*
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*
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* Initialize default command fields
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*
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* @param XTrafGen_Cmd is a pointer to command structure
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void InitDefaultCommands(XTrafGen_Cmd *CmdPtr)
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{
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/* Command RAM default command values */
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CmdPtr->CRamCmd.LastAddress = 0;
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CmdPtr->CRamCmd.Prot = 0;
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CmdPtr->CRamCmd.Id = 0;
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CmdPtr->CRamCmd.Size = 0x2;
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CmdPtr->CRamCmd.Burst = 0x1;
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CmdPtr->CRamCmd.Lock = 0;
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CmdPtr->CRamCmd.Length = 0;
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CmdPtr->CRamCmd.MyDepend = 0;
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CmdPtr->CRamCmd.OtherDepend = 0;
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CmdPtr->CRamCmd.MasterRamIndex = 0;
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CmdPtr->CRamCmd.Qos = 0;
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CmdPtr->CRamCmd.User = 0;
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CmdPtr->CRamCmd.Cache = 0;
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CmdPtr->CRamCmd.ExpectedResp = 0x7;
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/* Parameter RAM default command values */
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CmdPtr->PRamCmd.AddrMode = 0;
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CmdPtr->PRamCmd.IdMode = 0;
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CmdPtr->PRamCmd.IntervalMode = 0;
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CmdPtr->PRamCmd.OpCntl0 = 0;
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CmdPtr->PRamCmd.OpCntl1 = 0;
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CmdPtr->PRamCmd.OpCntl2 = 0;
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CmdPtr->PRamCmd.Opcode = 0;
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}
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