358 lines
11 KiB
Tcl
Executable file
358 lines
11 KiB
Tcl
Executable file
##############################################################################
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#
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# (c) Copyright 2004-2014 Xilinx, Inc. All rights reserved.
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#
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# This file contains confidential and proprietary information of Xilinx, Inc.
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# and is protected under U.S. and international copyright and other
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# intellectual property laws.
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#
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any rights to the
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# materials distributed herewith. Except as otherwise provided in a valid
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# license issued to you by Xilinx, and to the maximum extent permitted by
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# applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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# FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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# IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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# MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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# and (2) Xilinx shall not be liable (whether in contract or tort, including
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# negligence, or under any other theory of liability) for any loss or damage
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# of any kind or nature related to, arising under or in connection with these
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# materials, including for any direct, or any indirect, special, incidental,
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# or consequential loss or damage (including loss of data, profits, goodwill,
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# or any type of loss or damage suffered as a result of any action brought by
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# a third party) even if such damage or loss was reasonably foreseeable or
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# Xilinx had been advised of the possibility of the same.
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#
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# CRITICAL APPLICATIONS
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# Xilinx products are not designed or intended to be fail-safe, or for use in
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# any application requiring fail-safe performance, such as life-support or
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# safety devices or systems, Class III medical devices, nuclear facilities,
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# applications related to the deployment of airbags, or any other applications
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# that could lead to death, personal injury, or severe property or
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# environmental damage (individually and collectively, "Critical
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# Applications"). Customer assumes the sole risk and liability of any use of
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# Xilinx products in Critical Applications, subject only to applicable laws
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# and regulations governing limitations on product liability.
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#
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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# AT ALL TIMES.
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#
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# MODIFICATION HISTORY:
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# Ver Who Date Changes
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# -------- ------ -------- ----------------------------------------------------
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# 4.0 adk 10/12/13 Updated as per the New Tcl API's
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##############################################################################
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## @BEGIN_CHANGELOG EDK_I
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## - Add a new argument to gen_include_files.
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## @END_CHANGELOG
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## @BEGIN_CHANGELOG EDK_H
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##
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## - Added support for generation of multiple applications.
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## All TCL procedures are now required to have a software
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## project type as its first argument
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##
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## @END_CHANGELOG
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## @BEGIN_CHANGELOG EDK_M
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##
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## - Migrated to HAL phase 1 using new xil_testmem API.
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## - Added ECC support
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##
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## @END_CHANGELOG
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## @BEGIN_CHANGELOG EDK_P
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##
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## - Updated the logic which checks whether interrupt is connected
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##
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## @END_CHANGELOG
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# Uses $XILINX_EDK/bin/lib/xillib_sw.tcl
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# -----------------------------------------------------------------
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# Software Project Types (swproj):
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# 0 : MemoryTest - Calls basic memorytest routines from common driver dir
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# 1 : PeripheralTest - Calls any existing polled_example and/or selftest
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# -----------------------------------------------------------------
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# -----------------------------------------------------------------
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# Global variables
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# Each global string defined here is a C test function definition.
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# Each function defined here must have a unique function prototype.
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# Ie. ALL functions defined in this file must be capable of
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# co-existing in the same C file!
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# -----------------------------------------------------------------
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# TCL Procedures:
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# -----------------------------------------------------------------
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proc gen_include_files {swproj mhsinst} {
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if {$swproj == 1} {
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if {! [has_ecc_support $mhsinst]} {
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return ""
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}
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set bram_intr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
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if { ${bram_intr} == 1 } {
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set inc_file_lines {xbram.h bram_header.h bram_intr_header.h}
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} else {
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set inc_file_lines {xbram.h bram_header.h}
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}
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return $inc_file_lines
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}
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if {$swproj == 0} {
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set inc_file_lines {xil_testmem.h xstatus.h }
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return $inc_file_lines
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}
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return ""
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}
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proc gen_src_files {swproj mhsinst} {
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if {$swproj != 1 || ! [has_ecc_support $mhsinst]} {
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return ""
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}
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if {$swproj == 1} {
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set bram_intr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
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if { ${bram_intr} == 1 } {
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set inc_file_lines {examples/xbram_example.c examples/xbram_intr_example.c data/bram_header.h data/bram_intr_header.h}
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} else {
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set inc_file_lines {examples/xbram_example.c data/bram_header.h}
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}
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return $inc_file_lines
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}
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}
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proc gen_testfunc_def {swproj mhsinst} {
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return ""
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}
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proc gen_init_code {swproj mhsinst} {
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if {$swproj != 1 || ! [has_ecc_support $mhsinst]} {
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return ""
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}
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if {$swproj == 1} {
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set bram_intr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
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set ipname [get_property NAME $mhsinst]
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if { ${bram_intr} == 1 } {
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set decl " static XBram ${ipname}_Bram;"
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set inc_file_lines $decl
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return $inc_file_lines
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} else {
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return ""
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}
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}
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}
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proc gen_testfunc_call {swproj mhsinst} {
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if {$swproj == 1} {
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if {! [has_ecc_support $mhsinst]} {
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return ""
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}
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set ipname [get_property NAME $mhsinst]
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set deviceid [::hsi::utils::get_ip_param_name $mhsinst "DEVICE_ID"]
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set stdout [get_property CONFIG.STDOUT [get_os]]
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if { $stdout == "" || $stdout == "none" } {
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set hasStdout 0
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} else {
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set hasStdout 1
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}
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set bram_intr [::hsi::utils::is_ip_interrupting_current_proc $mhsinst]
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if { ${bram_intr} == 1 } {
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set intr_pin_name [get_pins -of_objects [get_cells $ipname] -filter "TYPE==INTERRUPT"]
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set intcname [::hsi::utils::get_connected_intr_cntrl $ipname $intr_pin_name]
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set intcvar intc
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set proc [get_sw_processor]
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set mbproc [string first "microblaze" $proc]
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set intr_port_name [get_intr_port_name $mhsinst]
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set intr_id "XPAR_${intcname}_${ipname}_${intr_port_name}_INTR"
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set intr_id [string toupper $intr_id]
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}
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set testfunc_call ""
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if {${hasStdout} == 0} {
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append testfunc_call "
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{
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int status;
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status = BramExample(${deviceid});
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}
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"
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if { ${bram_intr} == 1 } {
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append testfunc_call "
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{
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int Status;
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Status = BramIntrExample(&${intcvar}, \\
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&${ipname}_Bram, \\
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${deviceid}, \\
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${intr_id});
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}
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"
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}
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}
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if {${hasStdout} == 1} {
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append testfunc_call "
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{
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int status;
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print(\"\\r\\nRunning Bram Example() for ${ipname}...\\r\\n\");
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status = BramExample(${deviceid});
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if (status == 0) {
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xil_printf(\"Bram Example PASSED.\\r\\n\");
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}
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else {
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print(\"Bram Example FAILED.\\r\\n\");
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}
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}
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"
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if { ${bram_intr} == 1 } {
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append testfunc_call "
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{
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int Status;
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Status = BramIntrExample(&${intcvar}, \\
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&${ipname}_Bram, \\
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${deviceid}, \\
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${intr_id});
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if (Status == 0 ) {
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print(\"Bram Interrupt Test PASSED. \\r\\n\");
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}
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else {
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print(\"Bram Interrupt Test FAILED.\\r\\n\");
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}
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}
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"
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}
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}
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return $testfunc_call
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}
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set ipname [xget_value $mhsinst "NAME"]
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set hasStdout [xhas_stdout $mhsinst]
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set testfunc_call ""
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set prog_memranges [xget_program_mem_ranges $mhsinst]
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if {[string compare ${prog_memranges} ""] != 0} {
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foreach progmem $prog_memranges {
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set baseaddrval [xget_value $mhsinst "PARAMETER" ${progmem}]
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append testfunc_call "
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/*
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* MemoryTest routine will not be run for the memory at
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* ${baseaddrval} (${ipname})
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* because it is being used to hold a part of this application program
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*/
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"
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}
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}
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set romemranges [xget_readonly_mem_ranges $mhsinst]
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if {[string compare ${romemranges} ""] != 0} {
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foreach romem $romemranges {
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set baseaddrval [xget_value $mhsinst "PARAMETER" ${romem}]
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append testfunc_call "
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/*
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* MemoryTest routine will not be run for the memory at
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* ${baseaddrval} (${ipname})
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* because it is a read-only memory
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*/
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"
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}
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}
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set baseaddrs [xget_writeable_mem_ranges $mhsinst]
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if {[string compare ${baseaddrs} ""] == 0} {
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return $testfunc_call
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}
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append testfunc_call "
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/* Testing BRAM Memory (${ipname})*/
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\{"
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if {${hasStdout} == 1} {
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append testfunc_call "
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int status;"
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}
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# Get XPAR_ macro for each baseaddr param
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foreach baseaddr $baseaddrs {
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lappend baseaddr_macros [::hsi::utils::get_ip_param_name $mhsinst $baseaddr]
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}
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foreach baseaddr $baseaddr_macros {
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if {${hasStdout} == 0} {
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append testfunc_call "
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Xil_TestMem32((u32*)${baseaddr}, 512, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
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Xil_TestMem16((u16*)${baseaddr}, 1024, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
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Xil_TestMem8((u8*)${baseaddr}, 2048, 0xA5, XIL_TESTMEM_ALLMEMTESTS);"
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} else {
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append testfunc_call "
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print(\"Starting MemoryTest for ${ipname}:\\r\\n\");
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print(\" Running 32-bit test...\");
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status = Xil_TestMem32((u32*)${baseaddr}, 512, 0xAAAA5555, XIL_TESTMEM_ALLMEMTESTS);
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if (status == 0) {
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print(\"PASSED!\\r\\n\");
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}
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else {
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print(\"FAILED!\\r\\n\");
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}
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print(\" Running 16-bit test...\");
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status = Xil_TestMem16((u16*)${baseaddr}, 1024, 0xAA55, XIL_TESTMEM_ALLMEMTESTS);
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if (status == 0) {
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print(\"PASSED!\\r\\n\");
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}
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else {
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print(\"FAILED!\\r\\n\");
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}
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print(\" Running 8-bit test...\");
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status = Xil_TestMem8((u8*)${baseaddr}, 2048, 0xA5, XIL_TESTMEM_ALLMEMTESTS);
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if (status == 0) {
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print(\"PASSED!\\r\\n\");
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}
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else {
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print(\"FAILED!\\r\\n\");
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}"
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}
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}
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append testfunc_call "
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\}"
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return $testfunc_call
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}
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proc has_ecc_support {mhsinst} {
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set ecc [get_property CONFIG.C_ECC $mhsinst]
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if {$ecc != 0} {
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return 1
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}
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return 0
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}
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proc get_intr_port_name {mhsinst} {
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set ipname [get_property NAME $mhsinst]
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set port_intr [get_pins -of_objects [get_cells $mhsinst] "Interrupt"]
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if {$port_intr != ""} {
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return "INTERRUPT"
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}
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set port_intr [get_pins -of_objects [get_cells $mhsinst] "ECC_Interrupt"]
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if {$port_intr != ""} {
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return "ECC_INTERRUPT"
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}
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return "INTERRUPT"
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}
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