136 lines
6.3 KiB
C
136 lines
6.3 KiB
C
/*******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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*******************************************************************************/
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/******************************************************************************/
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/**
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*
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* @file xdptx_example_common.h
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*
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* Contains a design example using the XDptx driver. It performs a self test on
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* the DisplayPort TX core by training the main link at the maximum common
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* capabilities between the TX and RX and checking the lane status.
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*
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* @note The DisplayPort TX core does not work alone - video/audio
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* sources need to be set up in the system correctly, as well as
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* setting up the output path (for example, configuring the
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* hardware system with the DisplayPort TX core output to an FMC
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* card with DisplayPort output capabilities. Some platform
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* initialization will need to happen prior to calling XDptx driver
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* functions. See XAPP1178 as a reference.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.0 als 06/17/14 Initial creation.
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* </pre>
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*
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*******************************************************************************/
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#ifndef XDPTX_EXAMPLE_COMMON_H_
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/* Prevent circular inclusions by using protection macros. */
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#define XDPTX_EXAMPLE_COMMON_H_
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/******************************* Include Files ********************************/
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#include "xdptx.h"
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#include "xil_printf.h"
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#include "xil_types.h"
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#include "xparameters.h"
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#include "xstatus.h"
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/**************************** Constant Definitions ****************************/
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/* The unique device ID of the DisplayPort TX core instance to be used with the
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* examples. */
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#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
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/* If set to 1, the link training process will continue training despite failing
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* by attempting training at a reduced link rate. It will also continue
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* attempting to train the link at a reduced lane count if needed. With this
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* option enabled, link training will return failure only when all link rate and
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* lane count combinations have been exhausted - that is, training fails using
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* 1-lane and a 1.62Gbps link rate.
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* If set to 0, link training will return failure if the training failed using
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* the current lane count and link rate settings.
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* TRAIN_ADAPTIVE is used by the examples as input to the
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* XDptx_EnableTrainAdaptive driver function. */
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#define TRAIN_ADAPTIVE 1
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/* A value of 1 is used to indicate that the DisplayPort output path has a
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* redriver on the board that adjusts the voltage swing and pre-emphasis levels
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* that are outputted from the FPGA. If this is the case, the voltage swing and
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* pre-emphasis values supplied to the DisplayPort TX core will be evenly
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* distributed among the available levels as specified in the IP documentation.
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* Otherwise, a value of 0 is used to indicate that no redriver is present. In
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* order to meet the necessary voltage swing and pre-emphasis levels required by
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* a DisplayPort RX device, the level values specified to the DisplayPort TX
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* core will require some compensation.
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* TRAIN_HAS_REDRIVER is used by the examples as input to the
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* XDptx_SetHasRedriverInPath driver function.
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* Note: There are 16 possible voltage swing levels and 32 possible pre-emphasis
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* levels in the DisplayPort TX core that will be mapped to 4 possible
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* voltage swing and 4 possible pre-emphasis levels in the RX device. */
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#define TRAIN_HAS_REDRIVER 1
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/* The link rate setting to begin link training with. Valid values are:
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* XDPTX_LINK_BW_SET_540GBPS, XDPTX_LINK_BW_SET_270GBPS, and
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* XDPTX_LINK_BW_SET_162GBPS. */
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#define TRAIN_USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS
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/* The lane count setting to begin link training with. Valid values are:
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* XDPTX_LANE_COUNT_SET_4, XDPTX_LANE_COUNT_SET_2, and
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* XDPTX_LANE_COUNT_SET_1. */
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#define TRAIN_USE_LANE_COUNT XDPTX_LANE_COUNT_SET_4
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/* If set to 1, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will be ignored.
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* Instead, the maximum common link capabilities between the DisplayPort TX core
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* and the RX device will be used when establishing a link.
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* If set to 0, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will determine the
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* link rate and lane count settings that the link training process will begin
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* with. */
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#define TRAIN_USE_MAX_LINK 1
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/**************************** Function Prototypes *****************************/
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extern u32 Dptx_PlatformInit(void);
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extern u32 Dptx_StreamSrcSync(XDptx *InstancePtr);
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extern u32 Dptx_StreamSrcSetup(XDptx *InstancePtr);
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extern u32 Dptx_StreamSrcConfigure(XDptx *InstancePtr);
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u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId);
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u32 Dptx_StartLink(XDptx *InstancePtr);
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u32 Dptx_Run(XDptx *InstancePtr);
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/*************************** Variable Declarations ****************************/
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XDptx DptxInstance;
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#endif /* XDPTX_EXAMPLE_COMMON_H_ */
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