38d86a8508
This Patch modifies the TimeOut Register value,although timeout interrupt is not used, this register is changed to set to the maximum allowed HW timeout value. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
129 lines
4.3 KiB
C
Executable file
129 lines
4.3 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xiicps_selftest.c
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*
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* This component contains the implementation of selftest functions for the
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* XIicPs driver component.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- ---------------------------------------------
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* 1.00a drg/jz 01/30/10 First release
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* 1.00a sdm 09/22/11 Removed unused code
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* 2.4 sk 11/03/14 Removed TimeOut Register value check
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xiicps.h"
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/************************** Constant Definitions *****************************/
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#define REG_TEST_VALUE 0x00000005
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/**
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*
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* Runs a self-test on the driver/device. The self-test is destructive in that
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* a reset of the device is performed in order to check the reset values of
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* the registers and to get the device into a known state.
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*
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* Upon successful return from the self-test, the device is reset.
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*
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* @param InstancePtr is a pointer to the XIicPs instance.
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*
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* @return
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* - XST_SUCCESS if successful.
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* - XST_REGISTER_ERROR indicates a register did not read or write
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* correctly
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*
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* @note None.
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*
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******************************************************************************/
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int XIicPs_SelfTest(XIicPs *InstancePtr)
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{
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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/*
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* All the IIC registers should be in their default state right now.
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*/
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if ((XIICPS_CR_RESET_VALUE !=
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XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
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XIICPS_CR_OFFSET)) ||
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(XIICPS_IXR_ALL_INTR_MASK !=
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XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
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XIICPS_IMR_OFFSET))) {
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return XST_FAILURE;
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}
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XIicPs_Reset(InstancePtr);
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/*
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* Write, Read then write a register
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*/
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XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
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XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
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if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
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XIICPS_SLV_PAUSE_OFFSET)) {
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return XST_FAILURE;
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}
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XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
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XIICPS_SLV_PAUSE_OFFSET, 0);
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XIicPs_Reset(InstancePtr);
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return XST_SUCCESS;
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}
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