2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
531 lines
10 KiB
C
Executable file
531 lines
10 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2007 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xhwicap_clb_ff.h
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*
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* This header file contains bit information about the CLB FF resource.
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* This header file can be used with the XHwIcap_GetClbBits() and
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* XHwIcap_SetClbBits() functions.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a bjb 11/14/03 First release
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* 1.01a bjb 04/10/06 V4 Support
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* 2.00a ecm 10/20/07 V5 Support
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* </pre>
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*
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*****************************************************************************/
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#ifndef XHWICAP_CLB_FF_H_ /* prevent circular inclusions */
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#define XHWICAP_CLB_FF_H_ /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if XHI_FAMILY == XHI_DEV_FAMILY_V4 /* Virtex4 */
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/************************** Constant Definitions ****************************/
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/**
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* Index into the CONTENTS and SRMODE for XQ Register.
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*/
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#define XHI_CLB_XQ 0
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/**
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* Index into the CONTENTS and SRMODE for YQ Register.
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*/
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#define XHI_CLB_YQ 1
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/**************************** Type Definitions ******************************/
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typedef struct {
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/**
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* MODE values.
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*/
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const u8 LATCH[1]; /**< Value to put register into LATCH mode */
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const u8 FF[1]; /**< Value to put register into FF mode */
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/**
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* CONTENTS values.
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*/
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const u8 INIT0[1]; /**< Value to initialize register CONTENTS to 0 */
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const u8 INIT1[1]; /**< Value to initialize register CONTENTS to 1 */
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const u8 ZERO[1]; /**< Same as INIT0 */
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const u8 ONE[1]; /**< Same as INIT1 */
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/**
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* SRMODE values.
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*/
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const u8 SRLOW[1]; /**< When SR is asserted register goes to 0-Reset */
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const u8 SRHIGH[1]; /**< When SR is asserted register goes to 1-Set */
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/**
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* SYNCMODE values.
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*/
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const u8 SYNC[1]; /**< Puts XQ and YQ in synchronous set/reset mode */
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const u8 ASYNC[1]; /**< Puts XQ and YQ in asynchronous set/reset mode */
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/**
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* LATCH or FF mode. Indexed by slice (0-3) only.
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* It affects both XQ and YQ registers.
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*/
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const u8 MODE[4][1][2];
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/**
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* SYNC or ASYNC mode. Indexed by slice (0-3) only.
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* It affects both XQ and YQ registers.
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*/
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const u8 SYNCMODE[4][1][2];
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/**
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* INIT0, INIT1, ONE, or ZERO. Indexed by the slice basis (0-3).
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* And then indexed by the element (XHI_CLB_XQ or XHI_CLB_YQ).
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* INIT0 and ZERO are equivalent as well as INIT1 and ONE. There
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* are two values there only as to not confuse the values given in
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* FPGA_EDITOR which are INIT0 and INIT1. They both can either
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* initialize or directly set the Register contents (assuming a
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* GRESTORE packet command is used after doing a configuration on a
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* device).
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*/
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const u8 CONTENTS[4][2][1][2];
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/**
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* SRHIGH or SRLOW. Indexed by the slice (0-3).
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* And then indexed by the element (XHI_CLB_XQ or XHI_CLB_YQ)
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*/
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const u8 SRMODE[4][2][1][2];
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} XHwIcap_ClbFf;
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/***************** Macros (Inline Functions) Definitions ********************/
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/************************** Function Prototypes *****************************/
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/************************** Variable Definitions ****************************/
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/***************************************************************************/
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/**
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* This structure defines the bits associated with a Flip Flop in a CLB
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* tile. Note that there are 8 FFs, the XQ and YQ Registers in
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* Slice 0, 1, 2 and 3.
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*/
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const XHwIcap_ClbFf XHI_CLB_FF =
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{
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{1}, /* LATCH*/
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{0}, /* FF*/
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{1}, /* INIT0*/
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{0}, /* INIT1*/
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{1}, /* ZERO*/
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{0}, /* ONE*/
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{1}, /* SRLOW*/
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{0}, /* SRHIGH*/
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{1}, /* SYNC*/
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{0}, /* ASYNC*/
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/* MODE*/
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{
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/* Slice 0. */
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{
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{10, 20}
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},
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/* Slice 1. */
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{
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{50, 20}
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},
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/* Slice 2. */
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{
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{22, 20}
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},
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/* Slice 3. */
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{
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{62, 20}
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}
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},
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/* SYNCMODE*/
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{
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/* Slice 0. */
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{
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{26, 20}
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},
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/* Slice 1. */
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{
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{66, 20}
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},
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/* Slice 2. */
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{
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{25, 20}
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},
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/* Slice 3. */
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{
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{65, 20}
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}
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},
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/* CONTENTS*/
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{
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/* Slice 0. */
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{
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/* LE 0. */
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{
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{6, 20}
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},
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/* LE 1. */
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{
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{34, 20}
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}
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},
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/* Slice 1. */
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{
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/* LE 0. */
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{
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{46, 20}
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},
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/* LE 1. */
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{
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{74, 20}
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}
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},
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/* Slice 2. */
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{
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/* LE 0. */
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{
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{5, 20}
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},
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/* LE 1. */
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{
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{33, 20}
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}
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},
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/* Slice 3. */
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{
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/* LE 0. */
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{
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{45, 20}
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},
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/* LE 1. */
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{
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{73, 20}
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}
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}
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},
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/* SRMODE*/
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{
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/* Slice 0. */
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{
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/* LE 0. */
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{
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{0, 20}
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},
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/* LE 1. */
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{
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{30, 20}
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}
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},
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/* Slice 1. */
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{
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/* LE 0. */
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{
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{42, 20}
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},
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/* LE 1. */
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{
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{70, 20}
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}
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},
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/* Slice 2. */
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{
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/* LE 0. */
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{
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{1, 20}
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},
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/* LE 1. */
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{
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{29, 20}
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}
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},
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/* Slice 3. */
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{
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/* LE 0. */
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{
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{41, 20}
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},
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/* LE 1. */
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{
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{69, 20}
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}
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}
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},
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};
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#elif XHI_FAMILY == XHI_DEV_FAMILY_V5 /* Virtex5 */
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/************************** Constant Definitions ****************************/
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/**
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* Index into the CONTENTS and SRMODE for {A...D}Q Register.
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*/
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#define XHI_CLB_AQ 0
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#define XHI_CLB_BQ 1
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#define XHI_CLB_CQ 2
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#define XHI_CLB_DQ 3
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/**************************** Type Definitions ******************************/
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typedef struct {
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/**
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* MODE values.
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*/
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const u8 LATCH[1]; /**< Value to put register into LATCH mode */
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const u8 FF[1]; /**< Value to put register into FF mode */
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/**
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* CONTENTS values.
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*/
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const u8 INIT0[1]; /**< Value to initialize register CONTENTS to 0 */
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const u8 INIT1[1]; /**< Value to initialize register CONTENTS to 1 */
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const u8 ZERO[1]; /**< Same as INIT0 */
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const u8 ONE[1]; /**< Same as INIT1 */
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/**
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* SRMODE values.
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*/
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const u8 SRLOW[1]; /**< When SR is asserted register goes to 0-Reset */
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const u8 SRHIGH[1]; /**< When SR is asserted register goes to 1-Set */
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/**
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* SYNCMODE values.
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*/
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const u8 SYNC[1]; /**< Puts XQ and YQ in synchronous set/reset mode */
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const u8 ASYNC[1]; /**< Puts XQ and YQ in asynchronous set/reset mode */
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/**
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* LATCH or FF mode. Indexed by slice (0-1) only.
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* It affects both XQ and YQ registers.
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*/
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const u8 MODE[2][4][2];
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/**
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* SYNC or ASYNC mode. Indexed by slice (0-1) only.
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* It affects both XQ and YQ registers.
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*/
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const u8 SYNCMODE[2][4][2];
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/**
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* [type slice, L/M][num LUTS,4][num configs, 4]
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* INIT0, INIT1, ONE, or ZERO. Indexed by the slice basis (0-1).
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* And then indexed by the element (XHI_CLB_AQ .. XHI_CLB_DQ).
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* INIT0 and ZERO are equivalent as well as INIT1 and ONE. There
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* are two values there only as to not confuse the values given in
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* FPGA_EDITOR which are INIT0 and INIT1. They both can either
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* initialize or directly set the Register contents (assuming a
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* GRESTORE packet command is used after doing a configuration on a
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* device).
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*/
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const u8 CONTENTS[2][4][1][2];
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/**
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* [type slice, L/M][num LUTs 4][mode]
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* SRHIGH or SRLOW. Indexed by the slice (0-3).
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* And then indexed by the element (XHI_CLB_AQ ... XHI_CLB_DQ)
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*/
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const u8 SRMODE[2][4][1][2];
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} XHwIcap_ClbFf;
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/***************** Macros (Inline Functions) Definitions ********************/
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/************************** Function Prototypes *****************************/
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/************************** Variable Definitions ****************************/
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/***************************************************************************/
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/**
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* This structure defines the bits associated with a Flip Flop in a CLB
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* tile. Note that there are 8 FFs, the XQ and YQ Registers in
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* Slice 0, 1, 2 and 3.
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*/
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const XHwIcap_ClbFf XHI_CLB_FF =
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{
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{1}, /* LATCH*/
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{0}, /* FF*/
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{1}, /* INIT0*/
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{0}, /* INIT1*/
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{1}, /* ZERO*/
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{0}, /* ONE*/
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{1}, /* SRLOW*/
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{0}, /* SRHIGH*/
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{1}, /* SYNC*/
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{0}, /* ASYNC*/
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/* MODE*/
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{
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/* Slice 0. */
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{
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{0, 0},
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{0, 0},
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{0, 0},
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{0, 0}
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},
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/* Slice 1. */
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{
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{0, 0},
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{0, 0},
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{0, 0},
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{0, 0}
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}
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},
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/* SYNCMODE*/
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{
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/* Slice 0. */
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{
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{6, 0},
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{6, 0},
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{6, 0},
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{6, 0}
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},
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/* Slice 1. */
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{
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{6, 0},
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{6, 0},
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{6, 0},
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{6, 0}
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}
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},
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/* CONTENTS*/
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{
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/* Slice 0. */
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{
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/* LE 0. */
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{
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{6, 20}
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},
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/* LE 1. */
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{
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{6, 20}
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},
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/* LE 2. */
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{
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{6, 20}
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},
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/* LE 3. */
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{
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{6, 20}
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}
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},
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/* Slice 1. */
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{
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/* LE 0. */
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{
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{6, 20}
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},
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/* LE 1. */
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{
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{6, 20}
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},
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/* LE 2. */
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{
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{6, 20}
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},
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/* LE 3. */
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{
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{4, 20}
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}
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}
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},
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/* SRMODE*/
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{
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/* Slice 0. */
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{
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/* LE 0. */
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{
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{0, 20}
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},
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/* LE 1. */
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{
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{0, 20}
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},
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/* LE 2. */
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{
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{0, 20}
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},
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/* LE 3. */
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{
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{0, 20}
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}
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},
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/* Slice 1. */
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{
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/* LE 0. */
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{
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{2, 20}
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},
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/* LE 1. */
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{
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{2, 20}
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},
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/* LE 2. */
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{
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{2, 20}
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},
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/* LE 3. */
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{
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{0, 20}
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}
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}
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},
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};
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#else
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#error Unsupported FPGA Family
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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