6d847e63b2
When DRE is not enabled,adjust hsize and stride to memap data width on write channel(S2MM). On read channel(mm2s), adjust hsize to stream data width and stride to memap data width. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
183 lines
7.8 KiB
C
183 lines
7.8 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xaxivdma_i.h
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* @addtogroup axivdma_v6_0
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* @{
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*
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* Internal API definitions shared by driver files.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 08/18/10 First release
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* 2.00a jz 12/10/10 Added support for direct register access mode, v3 core
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* 2.01a jz 01/19/11 Added ability to re-assign BD addresses
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* Replaced include xenv.h with string.h in xaxivdma_i.h
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* file.
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* rkv 03/28/11 Added support for frame store register.
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* 3.00a srt 08/26/11 Added support for Flush on Frame Sync and dynamic
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* programming of Line Buffer Thresholds.
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* 4.00a srt 11/21/11 Added support for 32 Frame Stores and modified bit
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* mask of Park Offset Register.
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* Added support for GenLock & Fsync Source Selection.
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* 4.03a srt 01/18/13 - Added StreamWidth parameter to XAxiVdma_Channel
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* structure (CR 691866).
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* 4.04a srt 03/03/13 Support for the GenlockRepeat Control bit (Bit 15)
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* added in the new version of IP v5.04 (CR: 691391)
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* - Support for *_ENABLE_DEBUG_INFO_* debug configuration
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* parameters (CR: 703738)
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*
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* </pre>
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*
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*****************************************************************************/
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#ifndef XAXIVDMA_I_H_ /* prevent circular inclusions */
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#define XAXIVDMA_I_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <string.h> /* memset */
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#include "xil_types.h"
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#include "xdebug.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/* Buffer Descriptor (BD) is only visible in this file
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*/
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typedef u32 XAxiVdma_Bd[XAXIVDMA_BD_MINIMUM_ALIGNMENT_WD];
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/* The DMA channel is only visible to driver files
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*/
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typedef struct {
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u32 ChanBase; /* Base address for this channel */
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u32 InstanceBase; /* Base address for the whole device */
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u32 StartAddrBase; /* Start address register array base */
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int IsValid; /* Whether the channel has been initialized */
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int FlushonFsync; /* VDMA Transactions are flushed & channel states
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reset on Frame Sync */
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int HasSG; /* Whether hardware has SG engine */
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int IsRead; /* Read or write channel */
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int HasDRE; /* Whether support unaligned transfer */
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int LineBufDepth; /* Depth of Channel Line Buffer FIFO */
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int LineBufThreshold; /* Threshold point at which Channel Line
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* almost empty flag asserts high */
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int WordLength; /* Word length */
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int NumFrames; /* Number of frames to work on */
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UINTPTR HeadBdPhysAddr; /* Physical address of the first BD */
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UINTPTR HeadBdAddr; /* Virtual address of the first BD */
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UINTPTR TailBdPhysAddr; /* Physical address of the last BD */
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UINTPTR TailBdAddr; /* Virtual address of the last BD */
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int Hsize; /* Horizontal size */
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int Vsize; /* Vertical size saved for no-sg mode hw start */
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int AllCnt; /* Total number of BDs */
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int GenLock; /* Mm2s Gen Lock Mode */
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int S2MmSOF; /* S2MM Start of Flag */
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int StreamWidth; /* Stream Width */
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XAxiVdma_Bd BDs[XAXIVDMA_MAX_FRAMESTORE] __attribute__((__aligned__(32)));
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/*Statically allocated BDs */
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u32 DbgFeatureFlags; /* Debug Parameter Flags */
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int AddrWidth;
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int direction; /* Determines whether Read or write channel */
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}XAxiVdma_Channel;
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/* Duplicate layout of XAxiVdma_DmaSetup
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*
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* So to remove the dependency on xaxivdma.h
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*/
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typedef struct {
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int VertSizeInput; /**< Vertical size input */
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int HoriSizeInput; /**< Horizontal size input */
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int Stride; /**< Stride */
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int FrameDelay; /**< Frame Delay */
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int EnableCircularBuf; /**< Circular Buffer Mode? */
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int EnableSync; /**< Gen-Lock Mode? */
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int PointNum; /**< Master we synchronize with */
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int EnableFrameCounter; /**< Frame Counter Enable */
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UINTPTR FrameStoreStartAddr[XAXIVDMA_MAX_FRAMESTORE];
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/**< Start Addresses of Frame Store Buffers. */
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int FixedFrameStoreAddr;/**< Fixed Frame Store Address index */
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int GenLockRepeat; /**< Gen-Lock Repeat? */
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}XAxiVdma_ChannelSetup;
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/************************** Function Prototypes ******************************/
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/* Channel API
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*/
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void XAxiVdma_ChannelInit(XAxiVdma_Channel *Channel);
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void XAxiVdma_ChannelReset(XAxiVdma_Channel *Channel);
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int XAxiVdma_ChannelResetNotDone(XAxiVdma_Channel *Channel);
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int XAxiVdma_ChannelIsRunning(XAxiVdma_Channel *Channel);
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int XAxiVdma_ChannelIsBusy(XAxiVdma_Channel *Channel);
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u32 XAxiVdma_ChannelGetStatus(XAxiVdma_Channel *Channel);
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void XAxiVdma_ChannelRegisterDump(XAxiVdma_Channel *Channel);
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int XAxiVdma_ChannelStartParking(XAxiVdma_Channel *Channel);
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void XAxiVdma_ChannelStopParking(XAxiVdma_Channel *Channel);
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void XAxiVdma_ChannelStartFrmCntEnable(XAxiVdma_Channel *Channel);
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void XAxiVdma_ChannelEnableIntr(XAxiVdma_Channel *Channel, u32 IntrType);
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void XAxiVdma_ChannelDisableIntr(XAxiVdma_Channel *Channel, u32 IntrType);
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u32 XAxiVdma_ChannelGetPendingIntr(XAxiVdma_Channel *Channel);
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u32 XAxiVdma_ChannelGetEnabledIntr(XAxiVdma_Channel *Channel);
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void XAxiVdma_ChannelIntrClear(XAxiVdma_Channel *Channel, u32 IntrType);
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int XAxiVdma_ChannelStartTransfer(XAxiVdma_Channel *Channel,
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XAxiVdma_ChannelSetup *ChannelCfgPtr);
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int XAxiVdma_ChannelSetBdAddrs(XAxiVdma_Channel *Channel, UINTPTR BdAddrPhys,
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UINTPTR BdAddrVirt);
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int XAxiVdma_ChannelConfig(XAxiVdma_Channel *Channel,
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XAxiVdma_ChannelSetup *ChannelCfgPtr);
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int XAxiVdma_ChannelSetBufferAddr(XAxiVdma_Channel *Channel, UINTPTR *AddrSet,
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int NumFrames);
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int XAxiVdma_ChannelStart(XAxiVdma_Channel *Channel);
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void XAxiVdma_ChannelStop(XAxiVdma_Channel *Channel);
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int XAxiVdma_ChannelSetFrmCnt(XAxiVdma_Channel *Channel, u8 FrmCnt,
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u8 DlyCnt);
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void XAxiVdma_ChannelGetFrmCnt(XAxiVdma_Channel *Channel, u8 *FrmCnt,
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u8 *DlyCnt);
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u32 XAxiVdma_ChannelErrors(XAxiVdma_Channel *Channel);
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void XAxiVdma_ClearChannelErrors(XAxiVdma_Channel *Channel, u32 ErrorMask);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/** @} */
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