53ce20d940
Coefficient register base address offset changed in IP from 0x400 to 0x800 to accomodate all supported taps. Split Phase and Coefficient programming logic in 2 independent API's. For Bicubic and Bilinear scalers only Phase needs to be programmed. Signed-off-by: Rohit Consul <rohit.consul@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
77 lines
3.3 KiB
C
77 lines
3.3 KiB
C
// ==============================================================
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// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
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// Version: 2015.1
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// Copyright (C) 2015 Xilinx Inc. All rights reserved.
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//
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// ==============================================================
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// CTRL
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// 0x0000 : Control signals
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// bit 0 - ap_start (Read/Write/COH)
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// bit 1 - ap_done (Read/COR)
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// bit 2 - ap_idle (Read)
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// bit 3 - ap_ready (Read)
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// bit 7 - auto_restart (Read/Write)
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// others - reserved
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// 0x0004 : Global Interrupt Enable Register
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// bit 0 - Global Interrupt Enable (Read/Write)
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// others - reserved
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// 0x0008 : IP Interrupt Enable Register (Read/Write)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x000c : IP Interrupt Status Register (Read/TOW)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x0010 : Data signal of HwReg_Height
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// bit 15~0 - HwReg_Height[15:0] (Read/Write)
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// others - reserved
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// 0x0014 : reserved
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// 0x0018 : Data signal of HwReg_WidthIn
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// bit 15~0 - HwReg_WidthIn[15:0] (Read/Write)
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// others - reserved
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// 0x001c : reserved
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// 0x0020 : Data signal of HwReg_WidthOut
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// bit 15~0 - HwReg_WidthOut[15:0] (Read/Write)
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// others - reserved
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// 0x0024 : reserved
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// 0x0028 : Data signal of HwReg_ColorMode
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// bit 7~0 - HwReg_ColorMode[7:0] (Read/Write)
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// others - reserved
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// 0x002c : reserved
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// 0x0030 : Data signal of HwReg_PixelRate
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// bit 31~0 - HwReg_PixelRate[31:0] (Read/Write)
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// 0x0034 : reserved
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// 0x0400 ~
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// 0x07ff : Memory 'HwReg_hfltCoeff' (384 * 16b)
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// Word n : bit [15: 0] - HwReg_hfltCoeff[2n]
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// bit [31:16] - HwReg_hfltCoeff[2n+1]
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// 0x2000 ~
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// 0x3fff : Memory 'HwReg_phasesH_V' (1920 * 18b)
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// Word n : bit [17:0] - HwReg_phasesH_V[n]
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// others - reserved
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// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
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#define XV_HSCALER_CTRL_ADDR_AP_CTRL 0x0000
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#define XV_HSCALER_CTRL_ADDR_GIE 0x0004
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#define XV_HSCALER_CTRL_ADDR_IER 0x0008
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#define XV_HSCALER_CTRL_ADDR_ISR 0x000c
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#define XV_HSCALER_CTRL_ADDR_HWREG_HEIGHT_DATA 0x0010
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#define XV_HSCALER_CTRL_BITS_HWREG_HEIGHT_DATA 16
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#define XV_HSCALER_CTRL_ADDR_HWREG_WIDTHIN_DATA 0x0018
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#define XV_HSCALER_CTRL_BITS_HWREG_WIDTHIN_DATA 16
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#define XV_HSCALER_CTRL_ADDR_HWREG_WIDTHOUT_DATA 0x0020
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#define XV_HSCALER_CTRL_BITS_HWREG_WIDTHOUT_DATA 16
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#define XV_HSCALER_CTRL_ADDR_HWREG_COLORMODE_DATA 0x0028
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#define XV_HSCALER_CTRL_BITS_HWREG_COLORMODE_DATA 8
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#define XV_HSCALER_CTRL_ADDR_HWREG_PIXELRATE_DATA 0x0030
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#define XV_HSCALER_CTRL_BITS_HWREG_PIXELRATE_DATA 32
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#define XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_BASE 0x0800
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#define XV_HSCALER_CTRL_ADDR_HWREG_HFLTCOEFF_HIGH 0x0bff
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#define XV_HSCALER_CTRL_WIDTH_HWREG_HFLTCOEFF 16
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#define XV_HSCALER_CTRL_DEPTH_HWREG_HFLTCOEFF 384
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#define XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_BASE 0x2000
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#define XV_HSCALER_CTRL_ADDR_HWREG_PHASESH_V_HIGH 0x3fff
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#define XV_HSCALER_CTRL_WIDTH_HWREG_PHASESH_V 18
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#define XV_HSCALER_CTRL_DEPTH_HWREG_PHASESH_V 1920
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