
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
467 lines
14 KiB
C
Executable file
467 lines
14 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/******************************************************************************/
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/**
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* @file xusbps_intr.c
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*
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* This file contains the functions that are related to interrupt processing
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* for the EPB USB driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ----------------------------------------------------------
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* 1.00a jz 10/10/10 First release
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* 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
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* handling.
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* </pre>
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******************************************************************************/
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/***************************** Include Files **********************************/
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#include "xusbps.h"
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#include "xusbps_endpoint.h"
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/************************** Constant Definitions ******************************/
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/**************************** Type Definitions ********************************/
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/***************** Macros (Inline Functions) Definitions **********************/
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/************************** Variable Definitions ******************************/
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/************************** Function Prototypes *******************************/
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static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
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static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
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static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
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static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
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/*****************************************************************************/
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/**
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* This function is the first-level interrupt handler for the USB core. All USB
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* interrupts will be handled here. Depending on the type of the interrupt,
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* second level interrupt handler may be called. Second level interrupt
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* handlers will be registered by the user using the:
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* XUsbPs_IntrSetHandler()
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* and/or
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* XUsbPs_EpSetHandler()
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* functions.
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*
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*
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* @param HandlerRef is a Reference passed to the interrupt register
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* function. In our case this will be a pointer to the XUsbPs
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* instance.
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*
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* @return None
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*
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* @note None
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*
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******************************************************************************/
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void XUsbPs_IntrHandler(void *HandlerRef)
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{
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XUsbPs *InstancePtr;
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u32 IrqSts;
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Xil_AssertVoid(HandlerRef != NULL);
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InstancePtr = (XUsbPs *) HandlerRef;
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/* Handle controller (non-endpoint) related interrupts. */
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IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_ISR_OFFSET);
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/* Clear the interrupt status register. */
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XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
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XUSBPS_ISR_OFFSET, IrqSts);
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/* Nak interrupt, used to respond to host's IN request */
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if(IrqSts & XUSBPS_IXR_NAK_MASK) {
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/* Ack the hardware */
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XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPNAKISR_OFFSET,
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XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPNAKISR_OFFSET));
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}
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/***************************************************************
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*
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* Handle general interrupts. Endpoint interrupts will be handler
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* later.
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*
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*/
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/* RESET interrupt.*/
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if (IrqSts & XUSBPS_IXR_UR_MASK) {
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XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
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return;
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}
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/* Check if we have a user handler that needs to be called. Note that
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* this is the handler for general interrupts. Endpoint interrupts will
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* be handled below.
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*/
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if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
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(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
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}
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/***************************************************************
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*
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* Handle Endpoint interrupts.
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*
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*/
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if (IrqSts & XUSBPS_IXR_UI_MASK) {
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u32 EpStat;
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u32 EpCompl;
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/* ENDPOINT 0 SETUP PACKET HANDLING
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*
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* Check if we got a setup packet on endpoint 0. Currently we
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* only check for setup packets on endpoint 0 as we would not
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* expect setup packets on any other endpoint (even though it
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* is possible to send setup packets on other endpoints).
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*/
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EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPSTAT_OFFSET);
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if (EpStat & 0x0001) {
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/* Handle the setup packet */
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XUsbPs_IntrHandleEp0Setup(InstancePtr);
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/* Re-Prime the endpoint.
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* Endpoint is de-primed if a setup packet comes in.
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*/
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XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
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}
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/* Check for RX and TX complete interrupts. */
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EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPCOMPL_OFFSET);
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/* ACK the complete interrupts. */
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XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPCOMPL_OFFSET, EpCompl);
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/* Check OUT (RX) endpoints. */
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if (EpCompl & XUSBPS_EP_OUT_MASK) {
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XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
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}
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/* Check IN (TX) endpoints. */
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if (EpCompl & XUSBPS_EP_IN_MASK) {
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XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
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}
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}
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}
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/*****************************************************************************/
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/**
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* This function registers the user callback handler for controller
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* (non-endpoint) interrupts.
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*
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* @param InstancePtr is a pointer to the XUsbPs instance of the
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* controller.
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* @param CallBackFunc is the Callback function to register.
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* CallBackFunc may be NULL to clear the entry.
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* @param CallBackRef is the user data reference passed to the
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* callback function. CallBackRef may be NULL.
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* @param Mask is the User interrupt mask. Defines which interrupts
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* will cause the callback to be called.
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*
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* @return
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* - XST_SUCCESS: Callback registered successfully.
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* - XST_FAILURE: Callback could not be registered.
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*
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* @note None.
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*
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******************************************************************************/
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int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
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XUsbPs_IntrHandlerFunc CallBackFunc,
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void *CallBackRef, u32 Mask)
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{
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Xil_AssertNonvoid(InstancePtr != NULL);
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InstancePtr->HandlerFunc = CallBackFunc;
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InstancePtr->HandlerRef = CallBackRef;
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InstancePtr->HandlerMask = Mask;
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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* This function handles TX buffer interrupts. It is called by the interrupt
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* when a transmit complete interrupt occurs. It returns buffers of completed
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* descriptors to the caller.
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*
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* @param InstancePtr is a pointer to the XUsbPs instance of the
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* controller.
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* @param EpCompl is the Bit mask of endpoints that caused a transmit
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* complete interrupt.
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*
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* @return None
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*
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* @note None.
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*
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******************************************************************************/
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static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
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{
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int Index;
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u32 Mask;
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int NumEp;
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/* Check all endpoints for TX complete bits.
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*/
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Mask = 0x00010000;
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NumEp = InstancePtr->DeviceConfig.NumEndpoints;
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/* Check for every endpoint if its TX complete bit is
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* set.
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*/
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for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
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XUsbPs_EpIn *Ep;
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if (!(EpCompl & Mask)) {
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continue;
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}
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/* The TX complete bit for this endpoint is
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* set. Walk the list of descriptors to see
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* which ones are completed.
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*/
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Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
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while (Ep->dTDTail != Ep->dTDHead) {
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XUsbPs_dTDInvalidateCache(Ep->dTDTail);
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/* If the descriptor is not active then the buffer has
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* not been sent yet.
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*/
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if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
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break;
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}
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if (Ep->HandlerFunc) {
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void *BufPtr;
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BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
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XUSBPS_dTDUSERDATA);
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Ep->HandlerFunc(Ep->HandlerRef, Index,
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XUSBPS_EP_EVENT_DATA_TX,
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BufPtr);
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}
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Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
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}
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}
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}
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/*****************************************************************************/
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/**
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* This function handles RX buffer interrupts. It is called by the interrupt
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* when a receive complete interrupt occurs. It notifies the callback functions
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* that have been registered with the individual endpoints that data has been
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* received.
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*
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* @param InstancePtr
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* Pointer to the XUsbPs instance of the controller.
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*
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* @param EpCompl
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* Bit mask of endpoints that caused a receive complete interrupt.
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* @return
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* none
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*
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******************************************************************************/
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static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
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{
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XUsbPs_EpOut *Ep;
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int Index;
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u32 Mask;
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int NumEp;
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/* Check all endpoints for RX complete bits. */
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Mask = 0x00000001;
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NumEp = InstancePtr->DeviceConfig.NumEndpoints;
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/* Check for every endpoint if its RX complete bit is set.*/
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for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
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int numP = 0;
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if (!(EpCompl & Mask)) {
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continue;
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}
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Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
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XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
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/* Handle all finished dTDs */
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while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
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numP += 1;
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if (Ep->HandlerFunc) {
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Ep->HandlerFunc(Ep->HandlerRef, Index,
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XUSBPS_EP_EVENT_DATA_RX, NULL);
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}
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Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
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XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
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}
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/* Re-Prime the endpoint.*/
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XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
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}
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}
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/*****************************************************************************/
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/**
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* This function handles a RESET interrupt. It will notify the interrupt
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* handler callback of the RESET condition.
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*
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* @param InstancePtr is pointer to the XUsbPs instance of the controller
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* @param IrqSts is the Interrupt status register content.
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* To be passed on to the user.
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*
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* @return None
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*
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* @Note None.
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*
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******************************************************************************/
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static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
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{
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int Timeout;
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/* Clear all setup token semaphores by reading the
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* XUSBPS_EPSTAT_OFFSET register and writing its value back to
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* itself.
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*/
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XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
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XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPSTAT_OFFSET));
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/* Clear all the endpoint complete status bits by reading the
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* XUSBPS_EPCOMPL_OFFSET register and writings its value back
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* to itself.
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*/
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XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPCOMPL_OFFSET,
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XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPCOMPL_OFFSET));
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/* Cancel all endpoint prime status by waiting until all bits
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* in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
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* to XUSBPS_EPFLUSH_OFFSET.
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*
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* Avoid hanging here by using a Timeout counter...
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*/
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Timeout = XUSBPS_TIMEOUT_COUNTER;
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while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPPRIME_OFFSET) &
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XUSBPS_EP_ALL_MASK) && --Timeout) {
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/* NOP */
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}
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XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
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XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
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/* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
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* still set at this point. If the code gets to this point and
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* the reset bit has already been cleared we are in trouble and
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* hardware reset is necessary.
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*/
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if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
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XUSBPS_PORTSCR1_OFFSET) &
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XUSBPS_PORTSCR_PR_MASK)) {
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/* Send a notification to the user that a hardware
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* RESET is required. At this point we can only hope
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* that the user registered an interrupt handler and
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* will issue a hardware RESET.
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*/
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if (InstancePtr->HandlerFunc) {
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(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
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IrqSts);
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}
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else {
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for (;;);
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}
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/* If we get here there is nothing more to do. The user
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* should have reset the core.
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*/
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return;
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}
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/* Check if we have a user handler that needs to be called.
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*/
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if (InstancePtr->HandlerFunc) {
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(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
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}
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/* We are done. After RESET we don't proceed in the interrupt
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* handler.
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*/
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}
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/*****************************************************************************/
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/**
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* This function handles a Setup Packet interrupt. It will notify the interrupt
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* handler callback of the RESET condition.
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*
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* @param InstancePtr is a pointer to the XUsbPs instance of the
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* controller.
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*
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* @return None
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*
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* @Note None
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*
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******************************************************************************/
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static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
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{
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XUsbPs_EpOut *Ep;
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/* Notifiy the user. */
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Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
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if (Ep->HandlerFunc) {
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Ep->HandlerFunc(Ep->HandlerRef, 0,
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XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
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}
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}
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