2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
265 lines
8.5 KiB
C
Executable file
265 lines
8.5 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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* @file xaxipcie_ep_enable_example.c
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*
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* This file contains a design example for using AXI PCIe IP and its driver.
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*
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* The example handles AXI PCIe IP when it is configured as an end point.
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* It shows how to use the API's.
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*
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* @note
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*
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* This code will illustrate how the AXI Pcie IP and its standalone driver can
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* be used to:
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* - Initialize a AXI PCIe bridge core built as an end point
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* - Retrieve root complex configuration assigned to end point
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*
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* We tried to use as much of the driver's API calls as possible to show the
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* reader how each call could be used and that probably made the example not
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* the shortest way of doing the tasks shown as they could be done.
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*
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*<pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a rkv 03/07/11 Initial version based on PLB PCIE example
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* 2.00a rkv 10/19/11 Renamed function call XAxiPcie_GetRequestId to
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* XAxiPcie_GetRequesterId
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*
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*</pre>
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*****************************************************************************/
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/***************************** Include Files ********************************/
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#include "xparameters.h" /* Defines for XPAR constants */
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#include "xaxipcie.h" /* XAxiPcie interface */
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#include "stdio.h"
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/************************** Constant Definitions ****************************/
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/*
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* The following constants map to the XPAR parameters created in the
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* xparameters.h file. They are defined here such that a user can easily
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* change all the needed parameters in one place.
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*/
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#define AXIPCIE_DEVICE_ID XPAR_AXIPCIE_0_DEVICE_ID
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/*
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* Define the offsets within the PCIE configuration space from the beginning
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* of the PCIE configuration space.
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*/
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#define PCIE_CFG_ID_REG 0x0000 /* Vendor ID/Device ID
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* offset */
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#define PCIE_CFG_CMD_STATUS_REG 0x0001 /* Command/Status Register
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* Offset */
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#define PCIE_CFG_CAH_LAT_HD_REG 0x0003 /* Cache Line/Latency
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* Timer/Header Type/BIST
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* Register Offset */
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#define PCIE_CFG_BAR_ZERO_REG 0x0004 /* Bar 0 offset */
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#define PCIE_CFG_CMD_BUSM_EN 0x00000004 /* Bus master enable */
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/**************************** Type Definitions ******************************/
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#define printf xil_printf
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/***************** Macros (Inline Functions) Definitions ********************/
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/************************** Function Prototypes *****************************/
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int PCIeEndPointInitialize(XAxiPcie *XlnxEndPointPtr, u16 DeviceId);
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/************************** Variable Definitions ****************************/
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/* Allocate AXI PCIe End Point IP Instance */
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XAxiPcie XlnxEndPoint_0;
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/****************************************************************************/
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/**
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* This function is the entry point for PCIe End Point Example
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*
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* @param None
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*
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* @return - XST_SUCCESS if successful
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* - XST_FAILURE if unsuccessful
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*
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* @note None.
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*
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*****************************************************************************/
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int main(void)
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{
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int Status;
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/* Initialize End Point */
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Status = PCIeEndPointInitialize(&XlnxEndPoint_0,
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XPAR_AXIPCIE_0_DEVICE_ID);
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if (Status != XST_SUCCESS) {
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return (XST_FAILURE);
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}
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return(XST_SUCCESS);
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}
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/****************************************************************************/
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/**
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* This function initializes the AXI PCIE end point IP.
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*
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* @param XlnxEndPointPtr is a pointer to an instance of XAxiPcie data
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* structure represents an end point IP.
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* @param DeviceId is AXI PCIe IP unique Device Id
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*
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* @return - XST_SUCCESS if successful
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* - XST_FAILURE if unsuccessful
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*
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* @note None.
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*
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******************************************************************************/
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int PCIeEndPointInitialize(XAxiPcie *XlnxEndPointPtr, u16 DeviceId)
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{
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int Status;
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u32 HeaderData;
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u32 InterruptMask;
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u8 BusNum;
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u8 DeviceNum;
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u8 FunctionNum;
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u8 PortNumber;
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XAxiPcie_Config *ConfigPtr;
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/* Initialize the driver */
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ConfigPtr = XAxiPcie_LookupConfig(DeviceId);
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if (ConfigPtr == NULL) {
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printf("Failed to initialize PCIe End Point Instance\r\n");
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return XST_FAILURE;
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}
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Status = XAxiPcie_CfgInitialize(XlnxEndPointPtr, ConfigPtr,
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ConfigPtr->BaseAddress);
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if (Status != XST_SUCCESS) {
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printf("Failed to initialize PCIe End Point Instance\r\n");
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return XST_FAILURE;
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}
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/* See what interrupts are currently enabled */
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XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
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printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
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/* Disable.all interrupts */
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XAxiPcie_DisableInterrupts(XlnxEndPointPtr,
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XAXIPCIE_IM_ENABLE_ALL_MASK);
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/* See what interrupts are currently pending */
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XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
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printf("Interrupts currently pending are %8X\r\n", InterruptMask);
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/* Clear the pending interrupt */
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XAxiPcie_ClearPendingInterrupts(XlnxEndPointPtr,
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XAXIPCIE_ID_CLEAR_ALL_MASK);
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/*
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* Read enabled interrupts and pending interrupts to verify the
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* previous two operations and also to test those two API functions
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*/
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XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
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printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
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XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
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printf("Interrupts currently pending are %8X\r\n", InterruptMask);
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/* Make sure link is up. */
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Status = XAxiPcie_IsLinkUp(XlnxEndPointPtr);
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if (Status != TRUE ) {
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printf("Link is not up\r\n");
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return XST_FAILURE;
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}
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printf("Link is up\r\n");
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/* See if root complex has already configured this end point. */
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XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
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&HeaderData);
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printf("PCIe Command/Status Register is %08X\r\n", HeaderData);
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if (HeaderData & PCIE_CFG_CMD_BUSM_EN) {
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printf("Root Complex has configured this end point\r\n");
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}
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else {
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printf("Root Complex has NOT yet configured this end"
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" point\r\n");
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return XST_FAILURE;
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}
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XAxiPcie_GetRequesterId(XlnxEndPointPtr, &BusNum,
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&DeviceNum, &FunctionNum, &PortNumber);
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printf("Bus Number is %02X\r\n"
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"Device Number is %02X\r\n"
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"Function Number is %02X\r\n"
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"Port Number is %02X\r\n",
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BusNum, DeviceNum, FunctionNum, PortNumber);
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/* Read my configuration space */
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XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_ID_REG,
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&HeaderData);
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printf("PCIe Vendor ID/Device ID Register is %08X\r\n",
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HeaderData);
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XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
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&HeaderData);
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printf("PCIe Command/Status Register is %08X\r\n", HeaderData);
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XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CAH_LAT_HD_REG,
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&HeaderData);
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printf("PCIe Header Type/Latency Timer Register is %08X\r\n",
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HeaderData);
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XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_BAR_ZERO_REG,
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&HeaderData);
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printf("PCIe BAR 0 is %08X\r\n", HeaderData);
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return XST_SUCCESS;
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}
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