7e9c762d45
This patch updates the doxygen for the drivers axicdma,axidma, axipcie,axietherent,axipmon to include .h files in the listof files provided in the index.html file. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
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195 lines
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Xilinx Driver can v3_0: axicdma v3_0
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<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<hl>Software Drivers</hl>
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<h1>axicdma v3_0</h1><p>This is the driver API for the AXI CDMA engine.</p>
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<p>For a full description of the features of the AXI CDMA engine, please refer to the hardware specification. This driver supports the following features:</p>
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<ul>
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<li>Simple DMA transfer</li>
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<li>Scatter gather (SG) DMA transfer</li>
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<li>Interrupt for error or completion of transfers</li>
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<li>For SG DMA transfer:<ul>
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<li>Programmable interrupt coalescing</li>
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<li>Programmable delay timer counter</li>
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<li>Managing the buffer descriptors (BDs)</li>
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</ul>
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</li>
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</ul>
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<p><b>Two Hardware Building Modes</b></p>
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<p>The hardware can be built in two modes:</p>
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<ul>
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<li><b>Simple only mode</b>, in this mode, only simple transfers are supported by the hardware. The functionality is similar to the XPS Central DMA, however, the driver API to do the transfer is slightly different.</li>
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</ul>
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<ul>
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<li><b>Hybrid mode</b>, in this mode, the hardware supports both the simple transfer and the SG transfer. However, only one kind of transfer can be active at a time. If an SG transfer is ongoing in the hardware, a submission of a simple transfer fails. If a simple transfer is ongoing in the hardware, a submission of an SG transfer is successful, however the SG transfer will not start until the simple transfer is done.</li>
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</ul>
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<p><b>Transactions</b></p>
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<p>The hardware supports two types of transfers, the simple DMA transfer and the scatter gather (SG) DMA transfer.</p>
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<p>A simple DMA transfer only needs source buffer address, destination buffer address and transfer length to do a DMA transfer. Only one transfer can be submitted to the hardware at a time.</p>
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<p>A SG DMA transfer requires setting up a buffer descriptor (BD), which keeps the transfer information, including source buffer address, destination buffer address, and transfer length. The hardware updates the BD for the completion status of the transfer. BDs that are connected to each other can be submitted to the hardware at once, therefore, the SG DMA transfer has better performance when the application is doing multiple transfers each time.</p>
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<p><b>Callback Function</b></p>
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<p>Each transfer, for which the application cares about its completion, should provide with the driver its callback function. The signature of the callback function is as the following:</p>
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<p>void XAxiCdma_CallBackFn(void *CallBackRef, u32 IrqMask, int *NumPtr);</p>
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<p>Where the CallBackRef is a reference pointer that the application passes to the driver along with the callback function. The driver passes IrqMask to the application when it calls this callback. The NumPtr is only used in SG mode to track how many BDs still left for this callback function.</p>
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<p>The callback function is set upon transfer submission:</p>
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<ul>
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<li>Simple transfer callback function setup:</li>
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</ul>
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<p><b>Only set the callback function if in interrupt mode.</b></p>
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<p>For simple transfers, the callback function along with the callback reference pointer is passed to the driver through the submission of the simple transfer:</p>
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<p>XAxiCdma_SimpleTransfer(...)</p>
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<ul>
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<li>SG transfer callback function setup: For SG transfers, the callback function and the callback reference pointer are set through the transfer submission call:</li>
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</ul>
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<p>XAxiCdma_BdRingToHw(...)</p>
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<p><b>Simple Transfers</b></p>
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<p>For an application that only does one DMA transfer at a time, and the DMA engine is exclusively used by this application, simple DMA transfer is sufficient.</p>
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<p>Using the simple DMA transfer has the advantage of ease of use comparing to SG DMA transfer. For an individual DMA transfer, simple DMA transfer is also faster because of simplicity in software and hardware.</p>
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<p><b>Scatter Gather (SG) Transfers</b></p>
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<p>For an application that has multiple DMA transfers sometimes, or the DMA engine is shared by multiple applications, using SG DMA transfer yields better performance over all applications.</p>
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<p>The SG DMA transfer provides queuing of multiple transfers, therefore, it provides better performance because the hardware can continuously work on all submitted transfers without software intervention.</p>
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<p>The down side of using the SG DMA transfer is that you have to manage the memory for the buffer descriptors (BD), and setup BDs for the transfers.</p>
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<p><b>Interrupts</b></p>
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<p>The driver handles the interrupts.</p>
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<p>The completion of a transfer, that has a callback function associated with, will trigger the driver to call the callback function. The IrqMask that is passed through the callback function notifies the application about the completion status of the transfer.</p>
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<p><b>Interrupt Coalescing for SG Transfers</b></p>
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<p>For SG transfers, the application can program the interrupt coalescing threshold to reduce the frequency of interrupts. If the number of transfers does not match well with the interrupt coalescing threshold, the completion of the last transfer will not trigger the completion interrupt. However, after the specified delay count time, the delay interrupt will fire.</p>
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<p>By default, the interrupt threshold for the hardware is one, which is one interrupt per BD completion.</p>
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<p><b>Delay Interrupt for SG Transfers</b></p>
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<p>Delay interrupt is to signal the application about inactivity of transfers. If the delay interrupt is enabled, the delay timer starts counting down once a transfer has started. If the interval between transfers is longer than the delay counter, the delay interrupt is fired.</p>
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<p>By default, the delay counter is zero, which means the delay interrupt is disabled. To enable delay interrupt, the delay interrupt enable bit must be set and the delay counter must be set to a value between 1 to 255.</p>
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<p><b>BD management for SG DMA Transfers </b></p>
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<p>BD is shared by the software and the hardware. To use BD for SG DMA transfers, the application needs to use the driver API to do the following:</p>
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<ul>
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<li>Setup the BD ring:<ul>
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<li>XAxiCdma_BdRingCreate(...)</li>
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</ul>
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</li>
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</ul>
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<p>Note that the memory for the BD ring is allocated and is later de-allocated by the application.</p>
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<ul>
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<li>Request BD from the BD ring, more than one BDs can be requested at once:<ul>
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<li>XAxiCdma_BdRingAlloc(...)</li>
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</ul>
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</li>
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</ul>
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<ul>
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<li>Prepare BDs for the transfer, one BD at a time:<ul>
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<li>XAxiCdma_BdSetSrcBufAddr(...)</li>
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<li>XAxiCdma_BdSetDstBufAddr(...)</li>
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<li>XAxiCdma_BdSetLength(...)</li>
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</ul>
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</li>
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</ul>
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<ul>
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<li>Submit all prepared BDs to the hardware:<ul>
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<li>XAxiCdma_BdRingToHw(...)</li>
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</ul>
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</li>
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</ul>
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<ul>
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<li>Upon transfer completion, the application can request completed BDs from the hardware:<ul>
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<li>XAxiCdma_BdRingFromHw(...)</li>
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</ul>
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</li>
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</ul>
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<ul>
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<li>After the application has finished using the BDs, it should free the BDs back to the free pool:<ul>
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<li>XAxiCdma_BdRingFree(...)</li>
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</ul>
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</li>
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</ul>
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<p>The driver also provides API functions to get the status of a completed BD, along with get functions for other fields in the BD.</p>
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<p>The following two diagrams show the correct flow of BDs:</p>
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<p>The first diagram shows a complete cycle for BDs, starting from requesting the BDs to freeing the BDs. </p>
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<pre></pre><pre> <a class="el" href="xaxicdma_8h.html#a4b168a008bd2ea4a7797d60a716e29f6">XAxiCdma_BdRingAlloc()</a> <a class="el" href="xaxicdma_8h.html#a58faef3eda9fdbd9b368d66e55702258">XAxiCdma_BdRingToHw()</a>
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Free ------------------------> Pre-process ----------------------> Hardware
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/|\ |
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| <a class="el" href="xaxicdma_8h.html#a2447d02b1d2c12ec812746b452ff53cc">XAxiCdma_BdRingFree()</a> <a class="el" href="xaxicdma_8h.html#ae94bad12ae7b26d63871a6ed5e8593c6">XAxiCdma_BdRingFromHw()</a> |
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+--------------------------- Post-process <----------------------+</pre><pre> </pre><p>The second diagram shows when a DMA transfer is to be cancelled before enqueuing to the hardware, application can return the requested BDs to the free group using <a class="el" href="xaxicdma_8h.html#afa7e792362f65151e2f854731f3002c1">XAxiCdma_BdRingUnAlloc()</a>. </p>
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<pre></pre><pre> <a class="el" href="xaxicdma_8h.html#afa7e792362f65151e2f854731f3002c1">XAxiCdma_BdRingUnAlloc()</a>
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Free <----------------------- Pre-process</pre><pre> </pre><p><b>Physical/Virtual Addresses</b></p>
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<p>Addresses for the transfer buffers are physical addresses.</p>
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<p>For SG transfers, the next BD pointer in a BD is also a physical address.</p>
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<p>However, application's reference to a BD and to the transfer buffers are through virtual addresses.</p>
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<p>The application is responsible to translate the virtual addresses of its transfer buffers to physical addresses before handing them to the driver.</p>
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<p>For systems where MMU is not used, or MMU is a direct mapping, then the physical address and the virtual address are the same.</p>
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<p><b>Cache Coherency</b></p>
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<p>To prevent cache and memory inconsistency:</p>
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<ul>
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<li>Flush the transmit buffer range before the transfer</li>
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<li>Invalidate the receive buffer range before passing it to the hardware and before passing it to the application</li>
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</ul>
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<p>For SG transfers:</p>
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<ul>
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<li>Flush the BDs once the preparation setup is done</li>
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<li>Invalidate the memory region for BDs when BDs are retrieved from the hardware.</li>
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</ul>
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<p><b>BD alignment for SG Transfers</b></p>
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<p>The hardware has requirement for the minimum alignment of the BDs, XAXICDMA_BD_MINIMUM_ALIGNMENT. It is OK to have an alignment larger than the required minimum alignment, however, it must be multiple of the minimum alignment. The alignment is passed into <a class="el" href="xaxicdma_8h.html#a8c4e66e92f9739dd9de28d156e028c6b">XAxiCdma_BdRingCreate()</a>.</p>
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<p><b>Error Handling</b></p>
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<p>The hardware halts upon all error conditions. The driver will reset the hardware once the error occurs.</p>
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<p>The IrqMask argument in the callback function notifies the application about error conditions for the transfer.</p>
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<p><b>Mutual Exclusion</b></p>
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<p>The driver does not provide mutual exclusion mechanisms, it is up to the upper layer to handle this.</p>
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<p><b>Hardware Defaults & Exclusive Use</b></p>
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<p>The hardware is in the following condition on start or after a reset:</p>
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<ul>
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<li>All interrupts are disabled.</li>
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<li>The engine is in simple mode.</li>
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<li>Interrupt coalescing counter is one.</li>
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<li>Delay counter is 0.</li>
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</ul>
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<p>The driver has exclusive use of the hardware registers and BDs. Accessing the hardware registers or the BDs should always go through the driver API functions.</p>
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<p><b>Hardware Features That User Should Be Aware of</b></p>
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<p>For performance reasons, the driver does not check the submission of transfers during run time. It is the user's responsibility to submit approrpiate transfers to the hardware. The following hardware features should be considerred when submitting a transfer:</p>
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<p>. Whether the hardware supports unaligned transfers, reflected through C_INCLUDE_DRE in system.mhs file. Submitting unaligned transfers while the hardware does not support it, causes errors upon transfer submission. Aligned transfer is in respect to word length, and word length is defined through the building parameter XPAR_AXI_CDMA_0_M_AXI_DATA_WIDTH.</p>
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<p>. Memory range of the transfer addresses. Transfer data to executable memory can crash the system.</p>
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<p>. Lite mode. To save hardware resources (drastically), you may select "lite" mode build of the hardware. However, with lite mode, the following features are _not_ supported:</p>
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<ul>
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<li>Cross page boundary transfer. Each transfer must be restrictly inside one page; otherwise, slave error occurs.</li>
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<li>Unaligned transfer.</li>
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<li>Data width larger than 64 bit</li>
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<li>Maximum transfer length each time is limited to data_width * burst_len</li>
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</ul>
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<pre>
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MODIFICATION HISTORY:</pre><pre> . Updated the debug print on type casting to avoid warnings on u32. Cast
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u32 to (unsigned int) to use the x format.</pre><pre> Ver Who Date Changes
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----- ---- -------- -------------------------------------------------------
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1.00a jz 07/08/10 First release
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2.01a rkv 01/25/11 Added TCL script to generate Test App code for peripheral
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tests.
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Replaced with "\r\n" in place on "\n\r" in printf
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statements. Made some minor modifications for Doxygen
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2.02a srt 01/18/13 Added support for Key Hole feature (CR: 687217).
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Updated DDR base address for IPI designs (CR 703656).
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2.03a srt 04/13/13 Removed Warnings (CR 705006).
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Added logic to check if DDR is present in the test app
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tcl file. (CR 700806)
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3.0 adk 19/12/13 Updated as per the New Tcl API's
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</pre> </div>
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<p class="Copyright">
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Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
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