2dee01e56d
This patch updates the standalone files copyright information with the latest content. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
101 lines
3.4 KiB
C
101 lines
3.4 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file usleep.c
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*
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* This function provides a microsecond delay using the Global Timer register in
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* the ARM Cortex R5 MP core.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- -------- -------- -----------------------------------------------
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* 5.00 pkp 02/20/14 First release
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "sleep.h"
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#include "xtime_l.h"
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#include "xparameters.h"
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#include "xil_types.h"
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#include "xpseudo_asm.h"
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#include "xreg_cortexr5.h"
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/* Global Timer is always clocked at half of the CPU frequency */
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#define COUNTS_PER_USECOND 25U
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/*****************************************************************************/
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/**
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*
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* This API gives a delay in microseconds
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*
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* @param useconds requested
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*
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* @return 0 if the delay can be achieved, -1 if the requested delay
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* is out of range
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*
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* @note None.
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*
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****************************************************************************/
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s32 usleep(u32 useconds)
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{
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XTime tEnd, tCur;
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/*disable ttc timer*/
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Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x1U);
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/*set prescale value*/
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Xil_Out32(TTC3_BASEADDR + 0x00000000U, 0x000001U);
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/*write interval value to register*/
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Xil_Out32(TTC3_BASEADDR + 0x00000024U,0xFFFFFFFFU);
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/*write match value to register*/
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Xil_Out32(TTC3_BASEADDR + 0x00000030U,0xFFFFFFFFU);
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/* Enable ttc Timer */
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Xil_Out32(TTC3_BASEADDR + 0x0000000CU,0x1AU);
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XTime_GetTime(&tCur);
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tEnd = tCur + (((XTime) useconds) * (COUNTS_PER_USECOND));
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do
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{
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XTime_GetTime(&tCur);
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} while (tCur < tEnd);
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/* Disable ttc Timer */
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Xil_Out32(TTC3_BASEADDR + 0x0000000CU, Xil_In32(TTC3_BASEADDR + 0x0000000CU) | 0x00000001U);
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return 0;
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}
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