2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
662 lines
22 KiB
C
Executable file
662 lines
22 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xintc_l.c
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*
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* This file contains low-level driver functions that can be used to access the
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* device. The user should refer to the hardware device specification for more
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* details of the device operation.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00b jhl 04/24/02 First release
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* 1.00c rpm 10/17/03 New release. Support the static vector table created
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* in the xintc_g.c configuration table.
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* 1.00c rpm 04/09/04 Added conditional compilation around the old handler
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* XIntc_LowLevelInterruptHandler(). This handler will only
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* be include/compiled if XPAR_INTC_SINGLE_DEVICE_ID is
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* defined.
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* 1.10c mta 03/21/07 Updated to new coding style
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* 1.10c ecm 07/09/07 Read the ISR after the Acknowledge in the interrupt
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* handler to support architectures with posted write bus
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* access issues.
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* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs and _m is removed
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* from all the macro definitions.
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* 2.04a bss 01/13/12 Removed the unused Register variable for warnings.
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* 2.05a bss 08/18/12 Added XIntc_RegisterFastHandler API to register fast
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* interrupt handlers using base address.
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* 2.06a bss 01/28/13 To support Cascade mode:
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* Modified XIntc_DeviceInterruptHandler,
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* XIntc_SetIntrSvcOption,XIntc_RegisterHandler and
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* XIntc_RegisterFastHandler APIs.
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* Added XIntc_CascadeHandler API.
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* 2.07a bss 10/18/13 Modified XIntc_DeviceInterruptHandler to support
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* nested interrupts.
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*
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xparameters.h"
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xintc.h"
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#include "xintc_i.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress);
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#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
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static void XIntc_CascadeHandler(void *DeviceId);
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#endif
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/**
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*
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* This is the interrupt handler for the driver interface provided in this file
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* when there can be no argument passed to the handler. In this case, we just
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* use the globally defined device ID for the interrupt controller. This function
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* is provided mostly for backward compatibility. The user should use
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* XIntc_DeviceInterruptHandler() if possible.
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*
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* This function does not support multiple interrupt controller instances to be
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* handled.
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*
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* The user must connect this function to the interrupt system such that it is
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* called whenever the devices which are connected to it cause an interrupt.
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*
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* @return None.
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*
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* @note
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*
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* The constant XPAR_INTC_SINGLE_DEVICE_ID must be defined for this handler
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* to be included in the driver compilation.
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*
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******************************************************************************/
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#ifdef XPAR_INTC_SINGLE_DEVICE_ID
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void XIntc_LowLevelInterruptHandler(void)
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{
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/*
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* A level of indirection here because the interrupt handler used with
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* the driver interface given in this file needs to remain void - no
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* arguments. So we need the globally defined device ID of THE
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* interrupt controller.
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*/
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XIntc_DeviceInterruptHandler((void *) XPAR_INTC_SINGLE_DEVICE_ID);
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}
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#endif
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/*****************************************************************************/
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/**
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*
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* This function is the primary interrupt handler for the driver. It must be
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* connected to the interrupt source such that is called when an interrupt of
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* the interrupt controller is active. It will resolve which interrupts are
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* active and enabled and call the appropriate interrupt handler. It uses
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* the AckBeforeService flag in the configuration data to determine when to
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* acknowledge the interrupt. Highest priority interrupts are serviced first.
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* This function assumes that an interrupt vector table has been previously
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* initialized.It does not verify that entries in the table are valid before
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* calling an interrupt handler. In Cascade mode this function calls
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* XIntc_CascadeHandler to handle interrupts of Master and Slave controllers.
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* This functions also handles interrupts nesting by saving and restoring link
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* register of Microblaze and Interrupt Level register of interrupt controller
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* properly.
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* @param DeviceId is the zero-based device ID defined in xparameters.h
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* of the interrupting interrupt controller. It is used as a direct
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* index into the configuration data, which contains the vector
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* table for the interrupt controller. Note that even though the
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* argument is a void pointer, the value is not a pointer but the
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* actual device ID. The void pointer type is necessary to meet
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* the XInterruptHandler typedef for interrupt handlers.
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*
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* @return None.
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*
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* @note For nested interrupts, this function saves microblaze r14
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* register on entry and restores on exit. This is required since
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* compiler does not support nesting. This function enables
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* Microblaze interrupts after blocking further interrupts
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* from the current interrupt number and interrupts below current
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* interrupt proirity by writing to Interrupt Level Register of
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* INTC on entry. On exit, it disables microblaze interrupts and
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* restores ILR register default value(0xFFFFFFFF)back. It is
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* recommended to increase STACK_SIZE in linker script for nested
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* interrupts.
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*
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******************************************************************************/
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void XIntc_DeviceInterruptHandler(void *DeviceId)
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{
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u32 IntrStatus;
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u32 IntrMask = 1;
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int IntrNumber;
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XIntc_Config *CfgPtr;
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u32 Imr;
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/* Get the configuration data using the device ID */
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CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
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#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
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if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
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XIntc_CascadeHandler(DeviceId);
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}
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else
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#endif
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{ /* This extra brace is required for compilation in Cascade Mode */
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#if XPAR_XINTC_HAS_ILR == TRUE
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#ifdef __MICROBLAZE__
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volatile u32 R14_register;
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/* Save r14 register */
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R14_register = mfgpr(r14);
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#endif
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volatile u32 ILR_reg;
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/* Save ILR register */
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ILR_reg = Xil_In32(CfgPtr->BaseAddress + XIN_ILR_OFFSET);
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#endif
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/* Get the interrupts that are waiting to be serviced */
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IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
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/* Mask the Fast Interrupts */
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if (CfgPtr->FastIntr == TRUE) {
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Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
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IntrStatus &= ~Imr;
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}
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/* Service each interrupt that is active and enabled by
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* checking each bit in the register from LSB to MSB which
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* corresponds to an interrupt input signal
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*/
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for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs;
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IntrNumber++) {
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if (IntrStatus & 1) {
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XIntc_VectorTableEntry *TablePtr;
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#if XPAR_XINTC_HAS_ILR == TRUE
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/* Write to ILR the current interrupt
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* number
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*/
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Xil_Out32(CfgPtr->BaseAddress +
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XIN_ILR_OFFSET, IntrNumber);
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/* Read back ILR to ensure the value
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* has been updated and it is safe to
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* enable interrupts
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*/
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Xil_In32(CfgPtr->BaseAddress +
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XIN_ILR_OFFSET);
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/* Enable interrupts */
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Xil_ExceptionEnable();
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#endif
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/* If the interrupt has been setup to
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* acknowledge it before servicing the
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* interrupt, then ack it */
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if (CfgPtr->AckBeforeService & IntrMask) {
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XIntc_AckIntr(CfgPtr->BaseAddress,
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IntrMask);
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}
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/* The interrupt is active and enabled, call
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* the interrupt handler that was setup with
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* the specified parameter
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*/
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TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
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TablePtr->Handler(TablePtr->CallBackRef);
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/* If the interrupt has been setup to
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* acknowledge it after it has been serviced
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* then ack it
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*/
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if ((CfgPtr->AckBeforeService &
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IntrMask) == 0) {
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XIntc_AckIntr(CfgPtr->BaseAddress,
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IntrMask);
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}
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#if XPAR_XINTC_HAS_ILR == TRUE
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/* Disable interrupts */
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Xil_ExceptionDisable();
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/* Restore ILR */
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Xil_Out32(CfgPtr->BaseAddress + XIN_ILR_OFFSET,
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ILR_reg);
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#endif
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/*
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* Read the ISR again to handle architectures
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* with posted write bus access issues.
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*/
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XIntc_GetIntrStatus(CfgPtr->BaseAddress);
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/*
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* If only the highest priority interrupt is to
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* be serviced, exit loop and return after
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* servicing
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* the interrupt
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*/
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if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
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#if XPAR_XINTC_HAS_ILR == TRUE
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#ifdef __MICROBLAZE__
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/* Restore r14 */
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mtgpr(r14, R14_register);
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#endif
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#endif
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return;
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}
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}
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/* Move to the next interrupt to check */
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IntrMask <<= 1;
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IntrStatus >>= 1;
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/* If there are no other bits set indicating that all
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* interrupts have been serviced, then exit the loop
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*/
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if (IntrStatus == 0) {
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break;
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}
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}
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#if XPAR_XINTC_HAS_ILR == TRUE
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#ifdef __MICROBLAZE__
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/* Restore r14 */
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mtgpr(r14, R14_register);
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#endif
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#endif
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}
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}
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/*****************************************************************************/
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/**
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*
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* Set the interrupt service option, which can configure the driver so that it
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* services only a single interrupt at a time when an interrupt occurs, or
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* services all pending interrupts when an interrupt occurs. The default
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* behavior when using the driver interface given in xintc.h file is to service
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* only a single interrupt, whereas the default behavior when using the driver
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* interface given in this file is to service all outstanding interrupts when an
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* interrupt occurs. In Cascade mode same Option is set to Slave controllers.
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*
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* @param BaseAddress is the unique identifier for a device.
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* @param Option is XIN_SVC_SGL_ISR_OPTION if you want only a single
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* interrupt serviced when an interrupt occurs, or
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* XIN_SVC_ALL_ISRS_OPTION if you want all pending interrupts
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* serviced when an interrupt occurs.
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*
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* @return None.
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*
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* @note
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*
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* Note that this function has no effect if the input base address is invalid.
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*
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******************************************************************************/
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void XIntc_SetIntrSvcOption(u32 BaseAddress, int Option)
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{
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XIntc_Config *CfgPtr;
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CfgPtr = LookupConfigByBaseAddress(BaseAddress);
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if (CfgPtr != NULL) {
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CfgPtr->Options = Option;
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/* If Cascade mode set the option for all Slaves */
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if (CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
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int Index;
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for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1;
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Index++) {
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CfgPtr = XIntc_LookupConfig(Index);
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CfgPtr->Options = Option;
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}
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}
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}
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}
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/*****************************************************************************/
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/**
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*
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* Register a handler function for a specific interrupt ID. The vector table
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* of the interrupt controller is updated, overwriting any previous handler.
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* The handler function will be called when an interrupt occurs for the given
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* interrupt ID.
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*
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* This function can also be used to remove a handler from the vector table
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* by passing in the XIntc_DefaultHandler() as the handler and NULL as the
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* callback reference.
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* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
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* Controller
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*
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* @param BaseAddress is the base address of the interrupt controller
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* whose vector table will be modified.
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* @param InterruptId is the interrupt ID to be associated with the input
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* handler.
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* @param Handler is the function pointer that will be added to
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* the vector table for the given interrupt ID.
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* @param CallBackRef is the argument that will be passed to the new
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* handler function when it is called. This is user-specific.
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*
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* @return None.
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*
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* @note
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*
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* Note that this function has no effect if the input base address is invalid.
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*
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******************************************************************************/
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void XIntc_RegisterHandler(u32 BaseAddress, int InterruptId,
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XInterruptHandler Handler, void *CallBackRef)
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{
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XIntc_Config *CfgPtr;
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CfgPtr = LookupConfigByBaseAddress(BaseAddress);
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if (CfgPtr != NULL) {
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if (InterruptId > 31) {
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CfgPtr = XIntc_LookupConfig(InterruptId/32);
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CfgPtr->HandlerTable[InterruptId%32].Handler = Handler;
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CfgPtr->HandlerTable[InterruptId%32].CallBackRef =
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CallBackRef;
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}
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else {
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CfgPtr->HandlerTable[InterruptId].Handler = Handler;
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CfgPtr->HandlerTable[InterruptId].CallBackRef =
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CallBackRef;
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}
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}
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}
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/*****************************************************************************/
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/**
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*
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* Looks up the device configuration based on the base address of the device.
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* A table contains the configuration info for each device in the system.
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*
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* @param BaseAddress is the unique identifier for a device.
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*
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* @return
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*
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* A pointer to the configuration structure for the specified device, or
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* NULL if the device was not found.
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*
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* @note None.
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*
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******************************************************************************/
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static XIntc_Config *LookupConfigByBaseAddress(u32 BaseAddress)
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{
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XIntc_Config *CfgPtr = NULL;
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int Index;
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for (Index = 0; Index < XPAR_XINTC_NUM_INSTANCES; Index++) {
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if (XIntc_ConfigTable[Index].BaseAddress == BaseAddress) {
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CfgPtr = &XIntc_ConfigTable[Index];
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break;
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}
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}
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return CfgPtr;
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}
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/*****************************************************************************/
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/**
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*
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* Register a fast handler function for a specific interrupt ID. The handler
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* function will be called when an interrupt occurs for the given interrupt ID.
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* In Cascade mode Interrupt Id is used to set Handler for corresponding Slave
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* Controller
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*
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* @param BaseAddress is the base address of the interrupt controller
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* whose vector table will be modified.
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* @param InterruptId is the interrupt ID to be associated with the input
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* handler.
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* @param FastHandler is the function pointer that will be called when
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* interrupt occurs
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*
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* @return None.
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*
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* @note
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*
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* Note that this function has no effect if the input base address is invalid.
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*
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******************************************************************************/
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void XIntc_RegisterFastHandler(u32 BaseAddress, u8 Id,
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XFastInterruptHandler FastHandler)
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{
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u32 CurrentIER;
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u32 Mask;
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u32 Imr;
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XIntc_Config *CfgPtr;
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if (Id > 31) {
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/* Enable user required Id in Slave controller */
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CfgPtr = XIntc_LookupConfig(Id/32);
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/* Get the Enabled Interrupts */
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CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
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/* Convert from integer id to bit mask */
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Mask = XIntc_BitPosMask[(Id%32)];
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/* Disable the Interrupt if it was enabled before calling
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* this function
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*/
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if (CurrentIER & Mask) {
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XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
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(CurrentIER & ~Mask));
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}
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XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
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((Id%32) * 4), (u32) FastHandler);
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/* Slave controllers in Cascade Mode should have all as Fast
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* interrupts or Normal interrupts, mixed interrupts are not
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* supported
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*/
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XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
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/* Enable the Interrupt if it was enabled before calling this
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* function
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*/
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if (CurrentIER & Mask) {
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XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
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(CurrentIER | Mask));
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}
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}
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else {
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CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
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/* Convert from integer id to bit mask */
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Mask = XIntc_BitPosMask[Id];
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if (CurrentIER & Mask) {
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/* Disable Interrupt if it was enabled */
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CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
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XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
|
|
(CurrentIER & ~Mask));
|
|
}
|
|
|
|
XIntc_Out32(BaseAddress + XIN_IVAR_OFFSET + (Id * 4),
|
|
(u32) FastHandler);
|
|
|
|
Imr = XIntc_In32(BaseAddress + XIN_IMR_OFFSET);
|
|
XIntc_Out32(BaseAddress + XIN_IMR_OFFSET, Imr | Mask);
|
|
|
|
|
|
/* Enable Interrupt if it was enabled before calling
|
|
* this function
|
|
*/
|
|
if (CurrentIER & Mask) {
|
|
CurrentIER = XIntc_In32(BaseAddress + XIN_IER_OFFSET);
|
|
XIntc_Out32(BaseAddress + XIN_IER_OFFSET,
|
|
(CurrentIER | Mask));
|
|
}
|
|
}
|
|
}
|
|
|
|
#if XPAR_INTC_0_INTC_TYPE != XIN_INTC_NOCASCADE
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This function is called by primary interrupt handler for the driver to handle
|
|
* all Controllers in Cascade mode.It will resolve which interrupts are active
|
|
* and enabled and call the appropriate interrupt handler. It uses the
|
|
* AckBeforeService flag in the configuration data to determine when to
|
|
* acknowledge the interrupt. Highest priority interrupts are serviced first.
|
|
* This function assumes that an interrupt vector table has been previously
|
|
* initialized. It does not verify that entries in the table are valid before
|
|
* calling an interrupt handler.This function calls itself recursively to handle
|
|
* all interrupt controllers.
|
|
*
|
|
* @param DeviceId is the zero-based device ID defined in xparameters.h
|
|
* of the interrupting interrupt controller. It is used as a direct
|
|
* index into the configuration data, which contains the vector
|
|
* table for the interrupt controller.
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note
|
|
*
|
|
******************************************************************************/
|
|
static void XIntc_CascadeHandler(void *DeviceId)
|
|
{
|
|
u32 IntrStatus;
|
|
u32 IntrMask = 1;
|
|
int IntrNumber;
|
|
u32 Imr;
|
|
XIntc_Config *CfgPtr;
|
|
static int Id = 0;
|
|
|
|
/* Get the configuration data using the device ID */
|
|
CfgPtr = &XIntc_ConfigTable[(u32)DeviceId];
|
|
|
|
/* Get the interrupts that are waiting to be serviced */
|
|
IntrStatus = XIntc_GetIntrStatus(CfgPtr->BaseAddress);
|
|
|
|
/* Mask the Fast Interrupts */
|
|
if (CfgPtr->FastIntr == TRUE) {
|
|
Imr = XIntc_In32(CfgPtr->BaseAddress + XIN_IMR_OFFSET);
|
|
IntrStatus &= ~Imr;
|
|
}
|
|
|
|
/* Service each interrupt that is active and enabled by
|
|
* checking each bit in the register from LSB to MSB which
|
|
* corresponds to an interrupt input signal
|
|
*/
|
|
for (IntrNumber = 0; IntrNumber < CfgPtr->NumberofIntrs; IntrNumber++) {
|
|
if (IntrStatus & 1) {
|
|
XIntc_VectorTableEntry *TablePtr;
|
|
|
|
/* In Cascade mode call this function recursively
|
|
* for interrupt id 31 and until interrupts of last
|
|
* instance/controller are handled
|
|
*/
|
|
if ((IntrNumber == 31) &&
|
|
(CfgPtr->IntcType != XIN_INTC_LAST) &&
|
|
(CfgPtr->IntcType != XIN_INTC_NOCASCADE)) {
|
|
XIntc_CascadeHandler((void *)++Id);
|
|
Id--;
|
|
}
|
|
|
|
/* If the interrupt has been setup to
|
|
* acknowledge it before servicing the
|
|
* interrupt, then ack it */
|
|
if (CfgPtr->AckBeforeService & IntrMask) {
|
|
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
|
|
}
|
|
|
|
/* Handler of 31 interrupt Id has to be called only
|
|
* for Last controller in cascade Mode
|
|
*/
|
|
if (!((IntrNumber == 31) &&
|
|
(CfgPtr->IntcType != XIN_INTC_LAST) &&
|
|
(CfgPtr->IntcType != XIN_INTC_NOCASCADE))) {
|
|
|
|
/* The interrupt is active and enabled, call
|
|
* the interrupt handler that was setup with
|
|
* the specified parameter
|
|
*/
|
|
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
|
|
TablePtr->Handler(TablePtr->CallBackRef);
|
|
}
|
|
/* If the interrupt has been setup to acknowledge it
|
|
* after it has been serviced then ack it
|
|
*/
|
|
if ((CfgPtr->AckBeforeService & IntrMask) == 0) {
|
|
XIntc_AckIntr(CfgPtr->BaseAddress, IntrMask);
|
|
}
|
|
|
|
/*
|
|
* Read the ISR again to handle architectures with
|
|
* posted write bus access issues.
|
|
*/
|
|
XIntc_GetIntrStatus(CfgPtr->BaseAddress);
|
|
|
|
/*
|
|
* If only the highest priority interrupt is to be
|
|
* serviced, exit loop and return after servicing
|
|
* the interrupt
|
|
*/
|
|
if (CfgPtr->Options == XIN_SVC_SGL_ISR_OPTION) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Move to the next interrupt to check */
|
|
IntrMask <<= 1;
|
|
IntrStatus >>= 1;
|
|
|
|
/* If there are no other bits set indicating that all interrupts
|
|
* have been serviced, then exit the loop
|
|
*/
|
|
if (IntrStatus == 0) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
#endif
|