31d5d373fe
Added source files, integration files, self test example, mdd and tcl files to cfa driver. Signed-off-by: Shravan Kumar A <skumara@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
260 lines
8.8 KiB
C
Executable file
260 lines
8.8 KiB
C
Executable file
/******************************************************************************
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*
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* (c) Copyright 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xcfa_hw.h
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*
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* This header file contains identifiers and register-level driver functions (or
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* macros) that can be used to access the Xilinx Color Filter Array
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* Interpolation (CFA) core.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- -------------------------------------------------------
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* 7.0 adk 01/07/14 First release.
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* Added the register offsets and bit masks for the
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* registers and added backward compatibility for macros.
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* </pre>
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*
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******************************************************************************/
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#ifndef XCFA_HW_H_
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#define XCFA_HW_H_ /**< Prevent circular inclusions
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* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name General control registers offsets
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* @{
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*/
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#define XCFA_CONTROL_OFFSET 0x000 /**< Control */
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#define XCFA_STATUS_OFFSET 0x004 /**< Status */
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#define XCFA_ERROR_OFFSET 0x008 /**< Error */
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#define XCFA_IRQ_EN_OFFSET 0x00C /**< IRQ Enable */
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#define XCFA_VERSION_OFFSET 0x010 /**< Version */
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#define XCFA_SYSDEBUG0_OFFSET 0x014 /**< System Debug 0 */
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#define XCFA_SYSDEBUG1_OFFSET 0x018 /**< System Debug 1 */
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#define XCFA_SYSDEBUG2_OFFSET 0x01C /**< System Debug 2 */
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/* Timing control registers */
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#define XCFA_ACTIVE_SIZE_OFFSET 0x020 /**< Active Size (V x H) */
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/* Core specific registers offset */
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#define XCFA_BAYER_PHASE_OFFSET 0x100 /**< Bayer_phase RW user register */
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/*@}*/
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/** @name Control register bit mask definition
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* @{
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*/
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#define XCFA_CTL_SW_EN_MASK 0x00000001 /**< Enable Mask */
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#define XCFA_CTL_RUE_MASK 0x00000002 /**< Register Update Mask */
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#define XCFA_CTL_BPE_MASK 0x00000010 /**< Bypass Mask */
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#define XCFA_CTL_TPE_MASK 0x00000020 /**< Test pattern Mask */
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#define XCFA_CTL_AUTORESET_MASK 0x40000000 /**< Software Reset -
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* Auto-synchronize to SOF
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* Mask */
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#define XCFA_CTL_RESET_MASK 0x80000000 /**< Software Reset -
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* Instantaneous Mask */
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/*@}*/
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/** @name Interrupt Register Bit Masks. It is applicable for
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* Status and Irq_Enable Registers
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* @{
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*/
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#define XCFA_IXR_PROCS_STARTED_MASK 0x00000001 /**< Process Started
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* Mask */
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#define XCFA_IXR_EOF_MASK 0x00000002 /**< End-Of-Frame Mask */
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#define XCFA_IXR_SE_MASK 0x00010000 /**< Slave Error Mask */
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#define XCFA_IXR_ALLINTR_MASK 0x00010003 /**< Interrupt All Error Mask
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* (ORing of all
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* Interrupt Mask) */
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/*@}*/
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/** @name Error Register bit mask definitions
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* @{
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*/
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#define XCFA_ERR_EOL_EARLY_MASK 0x00000001 /**< Error: End of line
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* Early Mask */
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#define XCFA_ERR_EOL_LATE_MASK 0x00000002 /**< Error: End of line
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* Late Mask */
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#define XCFA_ERR_SOF_EARLY_MASK 0x00000004 /**< Error: Start of frame
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* Early Mask */
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#define XCFA_ERR_SOF_LATE_MASK 0x00000008 /**< Error: Start of frame
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* Late Mask */
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/*@}*/
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/** @name Version register bit definition and shifts
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* @{
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*/
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#define XCFA_VER_REV_NUM_MASK 0x000000FF /**< Revision Number Mask */
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#define XCFA_VER_PID_MASK 0x00000F00 /**< Patch ID Mask */
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#define XCFA_VER_MINOR_MASK 0x00FF0000 /**< Version Minor Mask */
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#define XCFA_VER_MAJOR_MASK 0xFF000000 /**< Version Major Mask */
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#define XCFA_VER_REV_MASK 0x0000F000 /**< Version revision Mask */
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#define XCFA_VER_MAJOR_SHIFT 24 /**< Version Major Shift */
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#define XCFA_VER_MINOR_SHIFT 16 /**< Version Minor Shift */
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#define XCFA_VER_INTERNAL_SHIFT 8 /**< Version Internal Shift */
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#define XCFA_VER_REV_SHIFT 12 /**< Version Revision Shift */
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/*@}*/
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/** @name Active size register bit mask definition and shifts
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* @{
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*/
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#define XCFA_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF /**< Active size
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* Mask */
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#define XCFA_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 /**< Number of Active
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* lines per
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* Frame
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* (Vertical) */
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#define XCFA_ACTSIZE_NUM_LINE_SHIFT 16 /**< Active size
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* Shift */
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/*@}*/
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/** @name Bayer Phase
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* @{
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*/
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#define XCFA_BAYER_PHASE_MASK 0x00000003 /**< Bayer Phase Mask */
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/*@}*/
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/** @name General purpose masks
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* @{
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*/
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#define XCFA_8_BIT_MASK 0x0FF /**< Generic 8 bit Mask */
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/*@}*/
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/** @name Backward compatibility macros
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* @{
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*/
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#define CFA_CONTROL XCFA_CONTROL_OFFSET
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#define CFA_STATUS XCFA_STATUS_OFFSET
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#define CFA_ERROR XCFA_ERROR_OFFSET
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#define CFA_IRQ_EN XCFA_IRQ_EN_OFFSET
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#define CFA_VERSION XCFA_VERSION_OFFSET
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#define CFA_SYSDEBUG0 XCFA_SYSDEBUG0_OFFSET
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#define CFA_SYSDEBUG1 XCFA_SYSDEBUG1_OFFSET
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#define CFA_SYSDEBUG2 XCFA_SYSDEBUG2_OFFSET
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#define CFA_ACTIVE_SIZE XCFA_ACTIVE_SIZE_OFFSET
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#define CFA_BAYER_PHASE XCFA_BAYER_PHASE_OFFSET
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#define CFA_CTL_EN_MASK XCFA_CTL_SW_EN_MASK
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#define CFA_CTL_RUE_MASK XCFA_CTL_RUE_MASK
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#define CFA_CTL_CS_MASK XCFA_CTL_CS_MASK
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#define CFA_RST_RESET XCFA_CTL_RESET_MASK
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#define CFA_RST_AUTORESET XCFA_CTL_AUTORESET_MASK
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#define CFA_In32 XCfa_In32
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#define CFA_Out32 XCfa_Out32
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#define CFA_ReadReg XCfa_ReadReg
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#define CFA_WriteReg XCfa_WriteReg
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/*@}*/
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/** @name Interrupt Enable and Status Registers Offsets
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* @{
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*/
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/**
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* Interrupt status register generates a interrupt if the corresponding bits of
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* interrupt enable register bits are set.
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*/
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#define XCFA_ISR_OFFSET XCFA_STATUS_OFFSET /**< Interrupt Status Offset */
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#define XCFA_IER_OFFSET XCFA_IRQ_EN_OFFSET /**< Interrupt Enable Offset */
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/*@}*/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XCfa_In32 Xil_In32 /**< Cfa Input Operation. */
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#define XCfa_Out32 Xil_Out32 /**< Cfa Output Operation. */
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/*****************************************************************************/
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/**
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*
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* This function macro reads the given register.
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*
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* @param BaseAddress is the base address of the CFA core.
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* @param RegOffset is the register offset of the core (defined at
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* top of this file).
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*
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* @return The 32-bit value of the register.
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*
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* @note C-style signature:
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* u32 XCfa_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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******************************************************************************/
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#define XCfa_ReadReg(BaseAddress, RegOffset) \
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XCfa_In32((BaseAddress) + (u32)(RegOffset))
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/*****************************************************************************/
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/**
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*
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* This function macro writes the given register.
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*
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* @param BaseAddress is the base address of the CFA core.
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* @param RegOffset is the register offset of the core (defined at
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* top of this file).
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* @param Data is the 32-bit value to write into the register.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XCfa_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
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*
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******************************************************************************/
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#define XCfa_WriteReg(BaseAddress, RegOffset, Data) \
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XCfa_Out32((BaseAddress) + (u32)(RegOffset), (Data))
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/**************************** Type Definitions *******************************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Declarations ****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* End of protection macro */
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