2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
290 lines
9.9 KiB
C
Executable file
290 lines
9.9 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xdmaps_hw.h
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*
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* This header file contains the hardware interface of an XDmaPs device.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ----------------------------------------------
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* 1.00a hbm 08/18/10 First Release
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* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
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* the maximum number of channels.
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* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
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* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
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* 1.02a sg 05/16/12 Made changes for doxygen
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* 1.06a kpc 07/10/13 Added function prototype
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* </pre>
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*
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******************************************************************************/
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#ifndef XDMAPS_HW_H /* prevent circular inclusions */
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#define XDMAPS_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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*
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* Register offsets for the DMAC.
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* @{
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*/
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#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
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#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
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#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
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#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
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#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
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*/
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#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
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#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
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* Register
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*/
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#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
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*/
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#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
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#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
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/*
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* The offset for the rest of the FTC registers is calculated as
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* FTC0 + dev_chan_num * 4
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*/
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#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
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#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
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/*
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* The offset for the rest of the CS registers is calculated as
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* CS0 + * dev_chan_num * 0x08
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*/
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#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
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#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
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* Channel 0
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*/
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/*
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* The offset for the rest of the CPC registers is calculated as
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* CPC0 + dev_chan_num * 0x08
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*/
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#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
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#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
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* Channel 0
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*/
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/* The offset for the rest of the SA registers is calculated as
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* SA_0 + dev_chan_num * 0x20
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*/
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#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
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#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
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* DMA Channel 0
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*/
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/* The offset for the rest of the DA registers is calculated as
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* DA_0 + dev_chan_num * 0x20
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*/
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#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
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#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
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* DMA Channel 0
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*/
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/*
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* The offset for the rest of the CC registers is calculated as
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* CC_0 + dev_chan_num * 0x20
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*/
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#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
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#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
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/*
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* The offset for the rest of the LC0 registers is calculated as
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* LC_0 + dev_chan_num * 0x20
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*/
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#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
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#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
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/*
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* The offset for the rest of the LC1 registers is calculated as
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* LC_0 + dev_chan_num * 0x20
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*/
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#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
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#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
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#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
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#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
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#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
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#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
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#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
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#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
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#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
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#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
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#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
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#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
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* Register 0
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*/
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#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
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* Register 1
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*/
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#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
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* Register 2
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*/
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#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
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* Register 3
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*/
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#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
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* Register 0
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*/
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#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
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* Register 1
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*/
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#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
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* Register 2
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*/
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#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
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* Register 3
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*/
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/*
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* Some useful register masks
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*/
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#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
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#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
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#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
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#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
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* llast 3 bits of CS register
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*/
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#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
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/*
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* XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
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* @b1: Instruction byte 1
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* @b0: Instruction byte 0
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* @ch: Channel number
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* @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
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*/
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#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
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(((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
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/* @} */
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/** @name Control Register
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*
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* The Control register (CR) controls the major functions of the device.
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*
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* Control Register Bit Definition
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*/
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/* @}*/
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#define XDMAPS_CHANNELS_PER_DEV 8
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/** @name Mode Register
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*
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* The mode register (MR) defines the mode of transfer as well as the data
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* format. If this register is modified during transmission or reception,
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* data validity cannot be guaranteed.
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*
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* Mode Register Bit Definition
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* @{
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*/
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/* @} */
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/** @name Interrupt Registers
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*
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* Interrupt control logic uses the interrupt enable register (IER) and the
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* interrupt disable register (IDR) to set the value of the bits in the
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* interrupt mask register (IMR). The IMR determines whether to pass an
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* interrupt to the interrupt status register (ISR).
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* Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
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* interrupt. IMR and ISR are read only, and IER and IDR are write only.
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* Reading either IER or IDR returns 0x00.
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*
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* All four registers have the same bit definitions.
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*
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* @{
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*/
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/* @} */
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#define XDMAPS_INTCLR_ALL_MASK 0xFF
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#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
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Xil_In32((BaseAddress) + (RegOffset))
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/***************************************************************************/
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/**
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* Write a DMAC register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the base address of the device.
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* @param RegisterValue is the value to be written to the register.
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*
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* @return None.
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*
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* @note
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* C-Style signature:
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* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
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* u32 RegisterValue)
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******************************************************************************/
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#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
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Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes *****************************/
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/*
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* Perform reset operation to the dmaps interface
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*/
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void XDmaPs_ResetHw(u32 BaseAddr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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