2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
325 lines
12 KiB
C
Executable file
325 lines
12 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/****************************************************************************/
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/**
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*
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* @file xaxipcie.h
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*
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* This file contains the software API definition of the Xilinx AXI PCIe IP
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* (XAxiPcie). This driver provides "C" function interface to application/upper
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* layer to access the hardware.
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*
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* <b>Features</b>
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* The driver provides its user with entry points
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* - To initialize and configure itself and the hardware
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* - To access PCIe configuration space locally
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* - To enable/disable and to report errors (interrupts).
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*
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* <b>IP Hardware Configuration</b>
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* The AXI PCIE IP supports only the endpoint for Virtex<65>-6 and Spartan<61>-6
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* families.
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*
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* The AXI PCIE IP supports both the endpoint and Root Port for the Kintex<65> 7
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* devices.
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*
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*
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* <b>Driver Initialization & Configuration</b>
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*
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* The XAxiPcie_Config structure is used by the driver to configure itself. This
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* configuration structure is typically created by the tool-chain based on HW
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* build properties.
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*
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* To support multiple runtime loading and initialization strategies employed
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* by various operating systems, the driver instance can be initialized in the
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* following way:
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*
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* - XAxiPcie_LookupConfig(DeviceId) - Use the device identifier to find the
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* static configuration structure defined in xaxipcie_g.c. This is setup by
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* the tools. For some operating systems the config structure will be
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* initialized by the software and this call is not needed.
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*
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* - XAxiPcie_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
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* configuration structure provided by the caller. If running in a system with
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* address translation, the provided virtual memory base address replaces the
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* physical address present in the configuration structure.
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*
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* <b>Interrupt Management</b>
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*
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* The XAxiPcie driver provides interrupt management functions. It allows
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* the caller to enable/disable each individual interrupt as well as get/clear
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* pending interrupts. Implementation of callback handlers is left to the user.
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*
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*
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* @note
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ------------------------------------------------------
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* 1.00a rkv 03/03/11 Original code.
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* 2.00a nm 10/19/11 Added support of pcie root complex functionality.
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* Changed these functions
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* -renamed function XAxiPcie_GetRequestId to
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* XAxiPcie_GetRequesterId
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* -added two functions arguments RootPortPtr &
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* ECAMSizePtr to XAxiPcie_GetBridgeInfo API
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* Added these new API for root complex support
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* - XAxiPcie_GetRootPortStatusCtrl
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* - XAxiPcie_SetRootPortStatusCtrl
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* - XAxiPcie_SetRootPortMSIBase
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* - XAxiPcie_GetRootPortErrFIFOMsg
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* - XAxiPcie_ClearRootPortErrFIFOMsg
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* - XAxiPcie_GetRootPortIntFIFOReg
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* - XAxiPcie_ClearRootPortIntFIFOReg
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* - XAxiPcie_WriteLocalConfigSpace
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* - XAxiPcie_ComposeExternalConfigAddress
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* - XAxiPcie_ReadRemoteConfigSpace
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* - XAxiPcie_WriteRemoteConfigSpace
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*
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* 2.01a nm 04/01/12 Removed XAxiPcie_SetRequesterId and
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* XAxiPcie_SetBlPortNumber APIs as these are writing
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* to Read Only bits for CR638299.
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* 2.02a nm 08/01/12 Updated for removing compilation errors with C++,
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* changed XCOMPONENT_IS_READY to XIL_COMPONENT_IS_READY
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* Removed the Endian Swap in
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* XAxiPcie_ReadRemoteConfigSpace and
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* XAxiPcie_WriteRemoteConfigSpace APIs as the HW
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* has been fixed and the swapping is not required
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* in the driver (CR 657412)
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* 2.03a srt 04/13/13 Removed Warnings (CR 705004).
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* 2.04a srt 09/06/13 Fixed CR 734175:
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* C_BASEADDR and C_HIGHADDR configuration parameters are
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* renamed to BASEADDR and HIGHADDR in Vivado builds.
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* Modified the tcl for this change.
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* 3.0 adk 19/12/13 Updated as per the New Tcl API's
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*
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* </pre>
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*
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*****************************************************************************/
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#ifndef XAXIPCIE_H /* prevent circular inclusions */
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#define XAXIPCIE_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files ********************************/
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#include "xil_assert.h"
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#include "xstatus.h"
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#include "xaxipcie_hw.h"
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#include "xil_types.h"
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#include <string.h>
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#include "xil_cache.h"
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/************************** Constant Definitions ****************************/
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/*
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* To figure out if PCIe IP
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* is configured as an end
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* point or as a root complex
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*/
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#define XAXIPCIE_IS_RC 0x01
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/*
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* 4KB alignment
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*/
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#define ALIGN_4KB 0xFFFFF000
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/*
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* Version Specific Enhanced Capability register numbers.
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*/
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#define XAXIPCIE_VSEC1 0x00 /**< First VSEC Register */
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#define XAXIPCIE_VSEC2 0x01 /**< Second VSEC Register */
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/**************************** Type Definitions ******************************/
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/**
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* This typedef contains IP hardware configuration information.
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*/
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typedef struct {
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u16 DeviceId; /**< Unique ID of PCIe IP */
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u32 BaseAddress; /**< Register base address */
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u8 LocalBarsNum; /* The number of local bus (AXI) BARs
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* in hardware
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*/
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u8 IncludeBarOffsetReg; /**<Are BAR Offset registers built in
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* hardware
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*/
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u8 IncludeRootComplex; /**< Is IP built as root complex */
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} XAxiPcie_Config;
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/**
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* The XAxiPcie driver instance data. The user is required to allocate a
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* variable of this type for every PCIe device in the system that will be
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* using this API. A pointer to a variable of this type is passed to the driver
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* API functions defined here.
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*/
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typedef struct {
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XAxiPcie_Config Config; /**< Configuration data */
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u32 IsReady; /**< Is IP been initialized and ready */
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u32 MaxNumOfBuses; /**< If this is RC IP, Max Number of
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* Buses */
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} XAxiPcie;
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/**
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* The user is required to use this strucuture when reading or writing
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* translation vector between local bus BARs and AXI PCIe BARs. It is used
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* when calling "XAxiPcie_GetLocalBusBar2PcieBar" and
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* "XAxiPcie_SetLocalBusBar2PcieBar" functions. The translation vectors are
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* 64 bits wide even though they might only use the lower 32 bits
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*/
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typedef struct {
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u32 LowerAddr; /**< Lower 32 bits of translation value */
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u32 UpperAddr; /**< Upper 32 bits of translation value */
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} XAxiPcie_BarAddr;
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/***************** Macros (Inline Functions) Definitions ********************/
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#ifndef XAxiPcie_GetRequestId
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#define XAxiPcie_GetRequestId XAxiPcie_GetRequesterId
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#endif
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/****************************************************************************/
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/**
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* Check whether link is up or not.
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*
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* @param InstancePtr is the XAxiPcie instance to operate on.
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*
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* @return
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* - TRUE if link is up
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* - FALSE if link is down
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*
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* @note None
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*
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*****************************************************************************/
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#define XAxiPcie_IsLinkUp(InstancePtr) \
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(XAxiPcie_ReadReg((InstancePtr)->Config.BaseAddress, \
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XAXIPCIE_PHYSC_OFFSET) & XAXIPCIE_PHYSC_LINK_UP_MASK) ? TRUE : FALSE
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/****************************************************************************/
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/**
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* Check whether ECAM is busy or not.
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*
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* @param InstancePtr is the XAxiPcie instance to operate on.
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*
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* @return
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* - TRUE if ECAM is busy
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* - FALSE if ECAM is idel
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*
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* @note This function is valid only when IP is configured as a
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* root complex
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*
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*****************************************************************************/
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#define XAxiPcie_IsEcamBusy(InstancePtr) \
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(XAxiPcie_ReadReg((InstancePtr)->Config.BaseAddress, \
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XAXIPCIE_BSC_OFFSET) & XAXIPCIE_BSC_ECAM_BUSY_MASK) ? TRUE : FALSE
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/************************** Function Prototypes *****************************/
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/*
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* API exported by the driver to the upper layer
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*
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* The following are the driver interface entry points.
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*
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*/
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/*
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* Config Look Up Function.
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* This API is implemented in xaxipcie_sinit.c
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*/
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XAxiPcie_Config * XAxiPcie_LookupConfig(u16 DeviceId);
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/*
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* PCIe Setup and Configuration Functions.
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* This API is implemented in xaxipcie.c
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*/
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/* Config Initialization */
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int XAxiPcie_CfgInitialize(XAxiPcie * InstancePtr, XAxiPcie_Config * CfgPtr,
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u32 EffectiveAddress);
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void XAxiPcie_GetVsecCapability(XAxiPcie *InstancePtr, u8 VsecNum,
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u16 *VsecIdPtr, u8 *VersionPtr, u16 *NextCapPtr);
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void XAxiPcie_GetVsecHeader(XAxiPcie *InstancePtr, u8 VsecNum, u16 *VsecIdPtr,
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u8 *RevisionPtr, u16 *LengthPtr);
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void XAxiPcie_GetBridgeInfo(XAxiPcie *InstancePtr, u8 *Gen2Ptr,
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u8 *RootPortPtr, u8 *ECAMSizePtr);
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void XAxiPcie_GetRequesterId(XAxiPcie *InstancePtr, u8 *BusNumPtr,
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u8 *DevNumPtr, u8 *FunNumPtr, u8 *PortNumPtr);
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void XAxiPcie_GetPhyStatusCtrl(XAxiPcie *InstancePtr, u32 *PhyState);
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void XAxiPcie_GetRootPortStatusCtrl(XAxiPcie *InstancePtr, u32 *StatusPtr);
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void XAxiPcie_SetRootPortStatusCtrl(XAxiPcie *InstancePtr, u32 StatusData);
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int XAxiPcie_SetRootPortMSIBase(XAxiPcie *InstancePtr,
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unsigned long long MsiBase);
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void XAxiPcie_GetRootPortErrFIFOMsg(XAxiPcie *InstancePtr, u16 *ReqIdPtr,
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u8 *ErrType, u8 *ErrValid);
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void XAxiPcie_ClearRootPortErrFIFOMsg(XAxiPcie *InstancePtr);
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int XAxiPcie_GetRootPortIntFIFOReg(XAxiPcie *InstancePtr, u16 *ReqIdPtr,
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u16 *MsiAddr, u8 *MsiInt, u8 *IntValid, u16 *MsiMsgData);
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void XAxiPcie_ClearRootPortIntFIFOReg(XAxiPcie *InstancePtr);
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void XAxiPcie_GetLocalBusBar2PcieBar(XAxiPcie *InstancePtr, u8 BarNumber,
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XAxiPcie_BarAddr *BarAddrPtr);
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void XAxiPcie_SetLocalBusBar2PcieBar(XAxiPcie *InstancePtr, u8 BarNumber,
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XAxiPcie_BarAddr *BarAddrPtr);
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void XAxiPcie_ReadLocalConfigSpace(XAxiPcie *InstancePtr, u16 Offset,
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u32 *DataPtr);
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void XAxiPcie_WriteLocalConfigSpace(XAxiPcie *InstancePtr, u16 Offset,
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u32 Data);
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void XAxiPcie_ReadRemoteConfigSpace(XAxiPcie *InstancePtr, u8 Bus, u8 Device,
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u8 Function, u16 Offset, u32 *DataPtr);
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void XAxiPcie_WriteRemoteConfigSpace(XAxiPcie *InstancePtr, u8 Bus, u8 Device,
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u8 Function, u16 Offset, u32 Data);
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/*
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* Interrupt Functions.
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* This API is implemented in xaxipcie_intr.c
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*/
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void XAxiPcie_EnableGlobalInterrupt(XAxiPcie *InstancePtr);
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void XAxiPcie_DisableGlobalInterrupt(XAxiPcie *InstancePtr);
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void XAxiPcie_EnableInterrupts(XAxiPcie *InstancePtr, u32 EnableMask);
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void XAxiPcie_DisableInterrupts(XAxiPcie *InstancePtr, u32 DisableMask);
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void XAxiPcie_GetEnabledInterrupts(XAxiPcie *InstancePtr, u32 *EnabledMaskPtr);
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void XAxiPcie_GetPendingInterrupts(XAxiPcie *InstancePtr, u32 *PendingMaskPtr);
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void XAxiPcie_ClearPendingInterrupts(XAxiPcie *InstancePtr, u32 ClearMask);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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