2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
363 lines
12 KiB
C
Executable file
363 lines
12 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xspi_l.h
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*
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* This header file contains identifiers, Register Definitions and basic driver
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* functions (or macros) that can be used to access the device.
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* Refer xspi.h for information about the driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00b rpm 04/24/02 First release
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* 1.11a wgr 03/22/07 Converted to new coding style.
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* 1.11a sv 02/22/08 Added the definition of LSB-MSB first option.
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* 1.12a sv 03/28/08 Removed macros in _l.h file, moved the
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* interrupt register definitions from _i.h to _l.h.
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* 2.00a sv 07/30/08 Removed macros in _l.h file, moved the
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* interrupt register definitions from _i.h to _l.h.
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* 3.00a ktn 10/28/09 Updated all the register accesses as 32 bit access.
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* Added XSpi_ReadReg and XSpi_WriteReg macros.
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* 3.01a sdm 04/23/10 Added definitions for the new slave mode interrupts.
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* 3.02a sdm 03/30/11 Added definitions for the new register bits in axi_qspi.
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* 3.04a bss 03/21/12 Added XIP Mode Register masks
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XSPI_L_H /* prevent circular inclusions */
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#define XSPI_L_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XSpi_In32 Xil_In32
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#define XSpi_Out32 Xil_Out32
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/****************************************************************************/
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/**
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*
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* Read from the specified Spi device register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to select the specific register.
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*
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* @return The value read from the register.
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*
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* @note C-Style signature:
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* u32 XSpi_ReadReg(u32 BaseAddress, u32 RegOffset);
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*
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******************************************************************************/
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#define XSpi_ReadReg(BaseAddress, RegOffset) \
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XSpi_In32((BaseAddress) + (RegOffset))
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/***************************************************************************/
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/**
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*
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* Write to the specified Spi device register.
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*
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* @param BaseAddress contains the base address of the device.
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* @param RegOffset contains the offset from the 1st register of the
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* device to select the specific register.
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* @param RegisterValue is the value to be written to the register.
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*
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* @return None.
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*
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* @note C-Style signature:
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* void XSpi_WriteReg(u32 BaseAddress, u32 RegOffset,
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* u32 RegisterValue);
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******************************************************************************/
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#define XSpi_WriteReg(BaseAddress, RegOffset, RegisterValue) \
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XSpi_Out32((BaseAddress) + (RegOffset), (RegisterValue))
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/************************** Function Prototypes ******************************/
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/************************** Constant Definitions *****************************/
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/**
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* XSPI register offsets
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*/
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/** @name Register Map
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*
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* Register offsets for the XSpi device.
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* @{
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*/
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#define XSP_DGIER_OFFSET 0x1C /**< Global Intr Enable Reg */
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#define XSP_IISR_OFFSET 0x20 /**< Interrupt status Reg */
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#define XSP_IIER_OFFSET 0x28 /**< Interrupt Enable Reg */
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#define XSP_SRR_OFFSET 0x40 /**< Software Reset register */
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#define XSP_CR_OFFSET 0x60 /**< Control register */
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#define XSP_SR_OFFSET 0x64 /**< Status Register */
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#define XSP_DTR_OFFSET 0x68 /**< Data transmit */
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#define XSP_DRR_OFFSET 0x6C /**< Data receive */
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#define XSP_SSR_OFFSET 0x70 /**< 32-bit slave select */
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#define XSP_TFO_OFFSET 0x74 /**< Tx FIFO occupancy */
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#define XSP_RFO_OFFSET 0x78 /**< Rx FIFO occupancy */
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/* @} */
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/**
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* @name Global Interrupt Enable Register (GIER) mask(s)
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* @{
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*/
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#define XSP_GINTR_ENABLE_MASK 0x80000000 /**< Global interrupt enable */
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/* @} */
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/** @name SPI Device Interrupt Status/Enable Registers
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*
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* <b> Interrupt Status Register (IPISR) </b>
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*
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* This register holds the interrupt status flags for the Spi device.
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*
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* <b> Interrupt Enable Register (IPIER) </b>
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*
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* This register is used to enable interrupt sources for the Spi device.
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* Writing a '1' to a bit in this register enables the corresponding Interrupt.
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* Writing a '0' to a bit in this register disables the corresponding Interrupt.
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*
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* ISR/IER registers have the same bit definitions and are only defined once.
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* @{
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*/
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#define XSP_INTR_MODE_FAULT_MASK 0x00000001 /**< Mode fault error */
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#define XSP_INTR_SLAVE_MODE_FAULT_MASK 0x00000002 /**< Selected as slave while
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* disabled */
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#define XSP_INTR_TX_EMPTY_MASK 0x00000004 /**< DTR/TxFIFO is empty */
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#define XSP_INTR_TX_UNDERRUN_MASK 0x00000008 /**< DTR/TxFIFO underrun */
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#define XSP_INTR_RX_FULL_MASK 0x00000010 /**< DRR/RxFIFO is full */
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#define XSP_INTR_RX_OVERRUN_MASK 0x00000020 /**< DRR/RxFIFO overrun */
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#define XSP_INTR_TX_HALF_EMPTY_MASK 0x00000040 /**< TxFIFO is half empty */
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#define XSP_INTR_SLAVE_MODE_MASK 0x00000080 /**< Slave select mode */
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#define XSP_INTR_RX_NOT_EMPTY_MASK 0x00000100 /**< RxFIFO not empty */
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/**
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* The following bits are available only in axi_qspi Interrupt Status and
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* Interrupt Enable registers.
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*/
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#define XSP_INTR_CPOL_CPHA_ERR_MASK 0x00000200 /**< CPOL/CPHA error */
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#define XSP_INTR_SLAVE_MODE_ERR_MASK 0x00000400 /**< Slave mode error */
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#define XSP_INTR_MSB_ERR_MASK 0x00000800 /**< MSB Error */
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#define XSP_INTR_LOOP_BACK_ERR_MASK 0x00001000 /**< Loop back error */
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#define XSP_INTR_CMD_ERR_MASK 0x00002000 /**< 'Invalid cmd' error */
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/**
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* Mask for all the interrupts in the IP Interrupt Registers.
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*/
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#define XSP_INTR_ALL (XSP_INTR_MODE_FAULT_MASK | \
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XSP_INTR_SLAVE_MODE_FAULT_MASK | \
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XSP_INTR_TX_EMPTY_MASK | \
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XSP_INTR_TX_UNDERRUN_MASK | \
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XSP_INTR_RX_FULL_MASK | \
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XSP_INTR_TX_HALF_EMPTY_MASK | \
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XSP_INTR_RX_OVERRUN_MASK | \
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XSP_INTR_SLAVE_MODE_MASK | \
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XSP_INTR_RX_NOT_EMPTY_MASK | \
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XSP_INTR_CMD_ERR_MASK | \
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XSP_INTR_LOOP_BACK_ERR_MASK | \
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XSP_INTR_MSB_ERR_MASK | \
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XSP_INTR_SLAVE_MODE_ERR_MASK | \
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XSP_INTR_CPOL_CPHA_ERR_MASK)
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/**
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* The interrupts we want at startup. We add the TX_EMPTY interrupt in later
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* when we're getting ready to transfer data. The others we don't care
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* about for now.
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*/
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#define XSP_INTR_DFT_MASK (XSP_INTR_MODE_FAULT_MASK | \
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XSP_INTR_TX_UNDERRUN_MASK | \
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XSP_INTR_RX_OVERRUN_MASK | \
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XSP_INTR_SLAVE_MODE_FAULT_MASK | \
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XSP_INTR_CMD_ERR_MASK)
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/* @} */
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/**
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* SPI Software Reset Register (SRR) mask.
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*/
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#define XSP_SRR_RESET_MASK 0x0000000A
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/** @name SPI Control Register (CR) masks
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*
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* @{
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*/
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#define XSP_CR_LOOPBACK_MASK 0x00000001 /**< Local loopback mode */
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#define XSP_CR_ENABLE_MASK 0x00000002 /**< System enable */
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#define XSP_CR_MASTER_MODE_MASK 0x00000004 /**< Enable master mode */
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#define XSP_CR_CLK_POLARITY_MASK 0x00000008 /**< Clock polarity high
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or low */
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#define XSP_CR_CLK_PHASE_MASK 0x00000010 /**< Clock phase 0 or 1 */
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#define XSP_CR_TXFIFO_RESET_MASK 0x00000020 /**< Reset transmit FIFO */
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#define XSP_CR_RXFIFO_RESET_MASK 0x00000040 /**< Reset receive FIFO */
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#define XSP_CR_MANUAL_SS_MASK 0x00000080 /**< Manual slave select
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assert */
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#define XSP_CR_TRANS_INHIBIT_MASK 0x00000100 /**< Master transaction
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inhibit */
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/**
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* LSB/MSB first data format select. The default data format is MSB first.
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* The LSB first data format is not available in all versions of the Xilinx Spi
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* Device whereas the MSB first data format is supported by all the versions of
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* the Xilinx Spi Devices. Please check the HW specification to see if this
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* feature is supported or not.
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*/
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#define XSP_CR_LSB_MSB_FIRST_MASK 0x00000200
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/* @} */
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/** @name SPI Control Register (CR) masks for XIP Mode
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*
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* @{
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*/
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#define XSP_CR_XIP_CLK_PHASE_MASK 0x00000001 /**< Clock phase 0 or 1 */
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#define XSP_CR_XIP_CLK_POLARITY_MASK 0x00000002 /**< Clock polarity
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high or low */
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/* @} */
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/** @name Status Register (SR) masks
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*
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* @{
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*/
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#define XSP_SR_RX_EMPTY_MASK 0x00000001 /**< Receive Reg/FIFO is empty */
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#define XSP_SR_RX_FULL_MASK 0x00000002 /**< Receive Reg/FIFO is full */
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#define XSP_SR_TX_EMPTY_MASK 0x00000004 /**< Transmit Reg/FIFO is
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empty */
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#define XSP_SR_TX_FULL_MASK 0x00000008 /**< Transmit Reg/FIFO is full */
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#define XSP_SR_MODE_FAULT_MASK 0x00000010 /**< Mode fault error */
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#define XSP_SR_SLAVE_MODE_MASK 0x00000020 /**< Slave mode select */
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/*
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* The following bits are available only in axi_qspi Status register.
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*/
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#define XSP_SR_CPOL_CPHA_ERR_MASK 0x00000040 /**< CPOL/CPHA error */
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#define XSP_SR_SLAVE_MODE_ERR_MASK 0x00000080 /**< Slave mode error */
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#define XSP_SR_MSB_ERR_MASK 0x00000100 /**< MSB Error */
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#define XSP_SR_LOOP_BACK_ERR_MASK 0x00000200 /**< Loop back error */
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#define XSP_SR_CMD_ERR_MASK 0x00000400 /**< 'Invalid cmd' error */
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/* @} */
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/** @name Status Register (SR) masks for XIP Mode
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*
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* @{
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*/
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#define XSP_SR_XIP_RX_EMPTY_MASK 0x00000001 /**< Receive Reg/FIFO
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is empty */
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#define XSP_SR_XIP_RX_FULL_MASK 0x00000002 /**< Receive Reg/FIFO
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is full */
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#define XSP_SR_XIP_MASTER_MODF_MASK 0x00000004 /**< Receive Reg/FIFO
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is full */
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#define XSP_SR_XIP_CPHPL_ERROR_MASK 0x00000008 /**< Clock Phase,Clock
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Polarity Error */
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#define XSP_SR_XIP_AXI_ERROR_MASK 0x00000010 /**< AXI Transaction
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Error */
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/* @} */
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/** @name SPI Transmit FIFO Occupancy (TFO) mask
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*
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* @{
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*/
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/* The binary value plus one yields the occupancy.*/
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#define XSP_TFO_MASK 0x0000001F
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/* @} */
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/** @name SPI Receive FIFO Occupancy (RFO) mask
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*
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* @{
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*/
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/* The binary value plus one yields the occupancy.*/
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#define XSP_RFO_MASK 0x0000001F
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/* @} */
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/** @name Data Width Definitions
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*
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* @{
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*/
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#define XSP_DATAWIDTH_BYTE 8 /**< Tx/Rx Reg is Byte Wide */
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#define XSP_DATAWIDTH_HALF_WORD 16 /**< Tx/Rx Reg is Half Word (16 bit)
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Wide */
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#define XSP_DATAWIDTH_WORD 32 /**< Tx/Rx Reg is Word (32 bit) Wide */
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/* @} */
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/** @name SPI Modes
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*
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* The following constants define the modes in which qxi_qspi operates.
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*
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* @{
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*/
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#define XSP_STANDARD_MODE 0
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#define XSP_DUAL_MODE 1
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#define XSP_QUAD_MODE 2
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/*@}*/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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