2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
302 lines
9.9 KiB
C
Executable file
302 lines
9.9 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xsrio_dma_loopback_example.c
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*
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* This file demonstrates how to use xsrio driver on the Xilinx SRIO Gen2 Core.
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* The SRIO Gen2 comprised of phy, logical and transport and buffer layers.
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* Using this IP We can generate both messaging and read/write semantics.
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*
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* This example demonstartes how to generate SWRITE(Streaming Write)
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* transactions on the core.
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*
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* Inorder to test this example external loopback is required at the boardlevel
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* Between the SRIO Tx and Rx pins.
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*
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* H/W Requirments:
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* Inorder to test this example at the h/w level the the SRIO Initiator Request
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* is connected to the AXI DMA MM2S Channel and SRIO Target Request is connected
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* to the AXI DMA S2MM Channel.
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*
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* S/W Flow:
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* 1) The system consists of two different memories.Processor runs this example
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* Code in one memory and the SRIO packet is formed in another memory.
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* 2) The SRIO Packet is framed in the Memory
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* 3) Configure the AXI DMA MM2S source address and S2MM for Destiantion address
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* and specify the byte count for both the channels and then start the dma.
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* 4) Compare the Data.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.0 adk 16/04/14 Initial release
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*
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* </pre>
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*
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* ***************************************************************************
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*/
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/***************************** Include Files *********************************/
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#include "xparameters.h"
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#include "xil_printf.h"
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#include "xil_types.h"
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#include "xstatus.h"
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#include "xsrio.h"
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#include "xbram.h"
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#include "xaxidma.h"
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define SRIO_DEVICE_ID XPAR_SRIO_0_DEVICE_ID
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#define MEM_ADDR XPAR_AXI_BRAM_CTRL_1_S_AXI_BASEADDR
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#define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID
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#define DATA_SIZE 256
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/******************** Variable Definitions **********************************/
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XSrio Srio; /* Instance of the XSrio */
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XAxiDma AxiDma; /* Instance of the XAxiDma */
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/******************** Function Prototypes ************************************/
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int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId);
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/*****************************************************************************/
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/**
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*
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* Main function
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*
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* This function is the main entry of the SRIO DMA Loopback test.
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*
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* @param None
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*
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* @return - XST_SUCCESS if tests pass
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* - XST_FAILURE if fails.
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*
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* @note None
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*
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******************************************************************************/
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int main()
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{
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int Status;
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xil_printf("Entering main\n\r");
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Status = XSrioDmaLoopbackExample(&Srio, SRIO_DEVICE_ID);
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if (Status != XST_SUCCESS) {
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xil_printf("SRIO DMA Loopback Test Failed\n\r");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_FAILURE;
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}
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xil_printf("SRIO DMA Loopback Test passed\n\r");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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* XSrioDmaLoopbackExample This function does a minimal test on the XSrio device
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* and driver as a design example. The purpose of this function is to illustrate
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* how to use the XSrio Component.
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*
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* This function does the following:
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* - Initialize the SRIO device
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* - Initialize the DMA engine
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* - Clearing the Memory
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* - Framing the SRIO Packet in the Memory
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* - Configuring the SRIO
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* - Configuring the DMA
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* - Verifying the Data
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*
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* @param InstancePtr is a pointer to the instance of the
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* XSrio driver.
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* @param DeviceId is Device ID of the SRIO Gen2 Device.
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*
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* @return -XST_SUCCESS to indicate success
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* -XST_FAILURE to indicate failure
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*
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******************************************************************************/
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int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId)
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{
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XSrio_Config *SrioConfig;
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XAxiDma_Config *DmaConfig;
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int Status = XST_SUCCESS;
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int Count = 0;
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/* Initialize the SRIO Device Configuration Interface driver */
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SrioConfig = XSrio_LookupConfig(DeviceId);
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if (!SrioConfig) {
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xil_printf("No SRIO config found for %d\r\n", DeviceId);
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return XST_FAILURE;
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}
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/**< This is where the virtual address would be used, this example
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* uses physical address.
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*/
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Status = XSrio_CfgInitialize(InstancePtr, SrioConfig,
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SrioConfig->BaseAddress);
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if (Status != XST_SUCCESS) {
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xil_printf("Initialization failed for SRIO\n\r");
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return Status;
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}
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/* Check for PE Configuration */
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Status = XSrio_GetPEType(InstancePtr);
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if (Status != XSRIO_IS_MEMORY) {
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xil_printf("SRIO is not configured as the Memory \n\r");
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return XST_FAILURE;
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}
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/* Clearing the Memory */
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for(Count=0; Count<(128*1024); Count += 4) {
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*(u32 *)(MEM_ADDR + Count) = 0;
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}
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/**< Check whether Streaming Write Operation is Supported by the
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* Core or not Since it is a loopback Example Checking at the both
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* Target and source Operations.
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*/
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Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
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XSRIO_DIR_TX);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
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XSRIO_DIR_RX);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/**< Frame the SRIO Write-Stream Packet in the Memory
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* The Packet-format used here is HELLO Packet format
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* More details look into pg 3.1 version:73 page(HELLO PACKET FORMAT).
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*/
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*(u32 *)(MEM_ADDR + 0x00) = 0x50000600; /**< Lower word of the
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* HELLO Packet
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*/
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*(u32 *)(MEM_ADDR + 0x04) = 0x08602F74; /**< Upper word of the
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* HELLO packet
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*/
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Count = 8;
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while(Count<(DATA_SIZE * 2)) {
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*(u32 *)(MEM_ADDR + Count) = Count;
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Count += 4;
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}
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/* SRIO Configuration */
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/* Set the Local Configuration Space Base Address */
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XSrio_SetLCSBA(InstancePtr, 0xFFF);
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/* Set the Water Mark Level to transfer priority 0,1,2 packet */
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XSrio_SetWaterMark(InstancePtr, 0x5, 0x4, 0x3);
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/* Set the Port Response timeout value */
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XSrio_SetPortRespTimeOutValue(InstancePtr, 0x010203);
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/* DMA Configuration */
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DmaConfig = XAxiDma_LookupConfig(DMA_DEV_ID);
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if (!DmaConfig) {
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xil_printf("No DMA config found for %d\r\n", DMA_DEV_ID);
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return XST_FAILURE;
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}
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/* Initialize DMA engine */
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Status = XAxiDma_CfgInitialize(&AxiDma, DmaConfig);
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if (Status != XST_SUCCESS) {
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xil_printf("Initialization failed %d\r\n", Status);
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return XST_FAILURE;
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}
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/**< Configure the DMA Tx Side
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* MEM_ADDR is the address where Tx packet is formed
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*/
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XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_CR_OFFSET,
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XAXIDMA_CR_RUNSTOP_MASK);
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XAxiDma_IntrEnable(&AxiDma,XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
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XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_SRCADDR_OFFSET, MEM_ADDR);
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/**< Configure the DMA Rx Side
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* MEM_ADDR+0x5000 is the address where Rx packet is formed
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*/
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XAxiDma_WriteReg(DmaConfig->BaseAddr,
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XAXIDMA_RX_OFFSET+XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK);
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XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
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XAxiDma_WriteReg(DmaConfig->BaseAddr,
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XAXIDMA_RX_OFFSET + XAXIDMA_DESTADDR_OFFSET, MEM_ADDR+0x5000);
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for(Count=8; Count<DATA_SIZE; Count += 4) {
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*(u32 *)(MEM_ADDR + Count) = Count;
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}
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XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_BUFFLEN_OFFSET, 256);
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/* Wait till DMA MM2S Transfer Complete */
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while(!(XAxiDma_ReadReg(DmaConfig->BaseAddr, XAXIDMA_SR_OFFSET)
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& 0x1000));
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XAxiDma_WriteReg(DmaConfig->BaseAddr,
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XAXIDMA_RX_OFFSET+XAXIDMA_BUFFLEN_OFFSET, 256);
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/* Wait till S2MM Transfer Complete */
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while(!( XAxiDma_ReadReg(DmaConfig->BaseAddr,
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XAXIDMA_RX_OFFSET+XAXIDMA_SR_OFFSET) & 0x1000));
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/* Verifying the Data */
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for(Count=8; Count<DATA_SIZE; Count += 4) {
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if(*(u32 *)(MEM_ADDR + 0x5000 + Count)
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!= *(u32 *)(MEM_ADDR + Count)) {
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xil_printf("\n ERROR in Transfer\n\r");
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return XST_FAILURE;
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}
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}
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/* Clearing the Memory */
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for(Count=0x5000; Count<(0x6000); Count += 4) {
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*(u32 *)(MEM_ADDR + Count) = 0;
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}
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for(Count=0; Count<DATA_SIZE; Count += 4) {
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if(*(u32 *)(MEM_ADDR + 0x5000+ Count) != 0x00) {
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xil_printf("\n ERROR in Clearing Memory\n\r");
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return XST_FAILURE;
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}
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}
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return Status;
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}
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