2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
570 lines
22 KiB
C
Executable file
570 lines
22 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xnandps_hw.h
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*
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* This file contains identifiers and low-level macros/functions for the NAND
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* Flash controller driver.
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* See xnandps.h for more information.
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*
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* @note None
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- ---------- -----------------------------------------------
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* 1.00a nm 12/10/2010 First release
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* </pre>
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*
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******************************************************************************/
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#ifndef XNANDPS_HW_H /* prevent circular inclusions */
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#define XNANDPS_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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/************************** Constant Definitions *****************************/
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/*
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* Memory controller configuration register offset
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*/
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#define XNANDPS_MEMC_STATUS_OFFSET 0x000 /**< Controller status
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reg, RO */
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#define XNANDPS_MEMC_IF_CONFIG_OFFSET 0x004 /**< Interface config
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reg, RO */
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#define XNANDPS_MEMC_SET_CONFIG_OFFSET 0x008 /**< Set configuration
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reg, WO */
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#define XNANDPS_MEMC_CLR_CONFIG_OFFSET 0x00C /**< Clear config reg,
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WO */
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#define XNANDPS_DIRECT_CMD_OFFSET 0x010 /**< Direct command
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reg, WO */
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#define XNANDPS_SET_CYCLES_OFFSET 0x014 /**< Set cycles
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register, WO */
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#define XNANDPS_SET_OPMODE_OFFSET 0x018 /**< Set opmode
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register, WO */
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#define XNANDPS_REFRESH_PERIOD_0_OFFSET 0x020 /**< Refresh period_0
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reg, RW */
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#define XNANDPS_REFRESH_PERIOD_1_OFFSET 0x024 /**< Refresh period_1
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reg, RW */
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/*
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* Chip configuration register offset
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*/
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#define XNANDPS_IF0_CHIP_0_CONFIG_OFFSET 0x100 /**< Interface 0 chip 0
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config */
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#define XNANDPS_IF0_CHIP_1_CONFIG_OFFSET 0x120 /**< Interface 0 chip 1
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config */
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#define XNANDPS_IF0_CHIP_2_CONFIG_OFFSET 0x140 /**< Interface 0 chip 2
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config */
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#define XNANDPS_IF0_CHIP_3_CONFIG_OFFSET 0x160 /**< Interface 0 chip 3
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config */
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#define XNANDPS_IF1_CHIP_0_CONFIG_OFFSET 0x180 /**< Interface 1 chip 0
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config */
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#define XNANDPS_IF1_CHIP_1_CONFIG_OFFSET 0x1A0 /**< Interface 1 chip 1
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config */
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#define XNANDPS_IF1_CHIP_2_CONFIG_OFFSET 0x1C0 /**< Interface 1 chip 2
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config */
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#define XNANDPS_IF1_CHIP_3_CONFIG_OFFSET 0x1E0 /**< Interface 1 chip 3
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config */
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/*
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* nand_cycles (RO), sram_cycles (RO) and opmode_x_n (RO) registers offsets
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*/
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#define XNANDPS_FLASH_CYCLES(addr) (0x000 + addr) /**< NAND & SRAM
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cycle,RO*/
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#define XNANDPS_OPMODE(addr) (0x004 + addr) /**< Chip opmode
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reg, RO */
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/*
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* User configuration register offset
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*/
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#define XNANDPS_USER_STATUS_OFFSET 0x200 /**< User status reg,
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RO */
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#define XNANDPS_USER_CONFIG_OFFSET 0x204 /**< User config reg,
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WO */
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/*
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* ECC register offset
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*/
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#define XNANDPS_IF0_ECC_OFFSET 0x300 /**< Interface 0 ECC
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register */
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#define XNANDPS_IF1_ECC_OFFSET 0x400 /**< Interface 1 ECC
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register */
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#define XNANDPS_ECC_STATUS_OFFSET(addr) (0x000 + addr) /**< ECC status
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register */
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#define XNANDPS_ECC_MEMCFG_OFFSET(addr) (0x004 + addr) /**< ECC mem
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config reg */
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#define XNANDPS_ECC_MEMCMD1_OFFSET(addr) (0x008 + addr) /**< ECC mem
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com1 reg*/
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#define XNANDPS_ECC_MEMCMD2_OFFSET(addr) (0x00C + addr) /**< ECC mem
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com2 reg*/
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#define XNANDPS_ECC_ADDR0_OFFSET(addr) (0x010 + addr) /**< ECC
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address0 reg
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*/
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#define XNANDPS_ECC_ADDR1_OFFSET(addr) (0x014 + addr) /**< ECC
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address1 reg
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*/
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#define XNANDPS_ECC_VALUE0_OFFSET(addr) (0x018 + addr) /**< ECC value 0
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reg */
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#define XNANDPS_ECC_VALUE1_OFFSET(addr) (0x01C + addr) /**< ECC value 1
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reg */
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#define XNANDPS_ECC_VALUE2_OFFSET(addr) (0x020 + addr) /**< ECC value 2
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reg */
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#define XNANDPS_ECC_VALUE3_OFFSET(addr) (0x024 + addr) /**< ECC value 3
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reg */
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#define XNANDPS_ECC_VALUE4_OFFSET(addr) (0x028 + addr) /**< ECC value 4
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reg */
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/*
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* Integration test register offset
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*/
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#define XNANDPS_INTGTEST_OFFSET 0xE00 /**< Integration test
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offset */
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/*
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* ID configuration register offset
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*/
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#define XNANDPS_PERIPH_ID0_OFFSET 0xFE0 /**< Peripheral id0
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register */
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#define XNANDPS_PERIPH_ID1_OFFSET 0xFE4 /**< Peripheral id1
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register */
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#define XNANDPS_PERIPH_ID2_OFFSET 0xFE8 /**< Peripheral id2
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register */
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#define XNANDPS_PERIPH_ID3_OFFSET 0xFEC /**< Peripheral id3
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register */
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#define XNANDPS_PCELL_ID0_OFFSET 0xFF0 /**< Primecell id0
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register */
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#define XNANDPS_PCELL_ID1_OFFSET 0xFF4 /**< Primecell id1
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register */
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#define XNANDPS_PCELL_ID2_OFFSET 0xFF8 /**< Primecell id2
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register */
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#define XNANDPS_PCELL_ID3_OFFSET 0xFFC /**< Primecell id3
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register */
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/** @name Memory controller status register bit definitions and masks
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* @{
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*/
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#define XNANDPS_MEMC_STATUS_STATE_MASK 0x00000001 /**< Memory
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controller operating state mask */
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#define XNANDPS_MEMC_STATUS_INT_EN0_MASK 0x00000002 /**< Memory
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controller interface 0 interrupt enable mask */
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#define XNANDPS_MEMC_STATUS_INT_EN1_MASK 0x00000004 /**< Memory
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controller interface 1 interrupt enable mask */
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#define XNANDPS_MEMC_STATUS_INT_STATUS0_MASK 0x00000008 /**< Memory
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controller interface 0 interrupt status mask */
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#define XNANDPS_MEMC_STATUS_INT_STATUS1_MASK 0x00000010 /**< Memory
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controller interface 1 interrupt status mask */
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#define XNANDPS_MEMC_STATUS_RAW_INT_STATUS0_MASK 0x00000020 /**< Memory
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controller interface 0 raw interrupt status mask */
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#define XNANDPS_MEMC_STATUS_RAW_INT_STATUS1_MASK 0x00000040 /**< Memory
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controller interface 1 raw interrupt status mask */
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#define XNANDPS_MEMC_STATUS_ECC_INT_EN0_MASK 0x00000080 /**< Memory
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controller interface 0 ECC interrupt enable mask */
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#define XNANDPS_MEMC_STATUS_ECC_INT_EN1_MASK 0x00000100 /**< Memory
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controller interface 1 ECC interrupt enable mask */
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#define XNANDPS_MEMC_STATUS_ECC_INT0_MASK 0x00000200 /**< Memory
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controller interface 0 ECC interrupt status mask */
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#define XNANDPS_MEMC_STATUS_ECC_INT1_MASK 0x00000400 /**< Memory
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controller interface 1 ECC interrupt status mask */
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#define XNANDPS_MEMC_STATUS_RAW_ECC_INT0_MASK 0x00000800 /**< Memory
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controller interface 0 raw ECC interrupt status mask */
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#define XNANDPS_MEMC_STATUS_RAW_ECC_INT1_MASK 0x00001000 /**< Memory
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controller interface 1 raw ECC interrupt status mask */
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/* @} */
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/** @name Memory interface configurartion register bit definitions and masks
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* @{
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*/
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#define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE0_MASK 0x00000003 /**< Memory
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controller interface 0 type mask */
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#define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS0_MASK 0x0000000C /**< Memory
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controller interface 0 chip select mask */
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#define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH0_MASK 0x00000030 /**< Memory
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controller interface 0 data width mask */
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#define XNANDPS_MEMC_IF_CONFIG_REMAP0_MASK 0x00000040 /**< Memory
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controller interface 0 remap0 mask */
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#define XNANDPS_MEMC_IF_CONFIG_MEMORY_TYPE1_MASK 0x00000300 /**< Memory
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controller interface 1 type mask */
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#define XNANDPS_MEMC_IF_CONFIG_MEMORY_CHIPS1_MASK 0x00000C00 /**< Memory
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controller interface 1 chip select mask */
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#define XNANDPS_MEMC_IF_CONFIG_MEMORY_WIDTH1_MASK 0x00003000 /**< Memory
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controller interface 1 data width mask */
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#define XNANDPS_MEMC_IF_CONFIG_REMAP1_MASK 0x00004000 /**< Memory
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controller interface 1 remap0 mask */
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#define XNANDPS_MEMC_IF_CONFIG_EX_MONITORS_MASK 0x00030000 /**< Memory
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controller interface exclusive masks mask */
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/* @} */
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/** @name Set configuration register bit definitions and masks
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* @{
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*/
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#define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE0_MASK 0x00000001 /**< Memory
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controller interfce0 interrupt enable mask */
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#define XNANDPS_MEMC_SET_CONFIG_INT_ENABLE1_MASK 0x00000002 /**< Memory
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controller interfce1 interrupt enable mask */
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#define XNANDPS_MEMC_SET_CONFIG_LOW_POWER_REQ_MASK 0x00000004 /**< Memory
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controller low power state mask */
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#define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE0_MASK 0x00000020 /**< Memory
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controller interfce0 ECC interrupt enable mask */
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#define XNANDPS_MEMC_SET_CONFIG_ECC_INT_ENABLE1_MASK 0x00000040 /**< Memory
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controller interfce1 ECC interrupt enable mask */
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/* @} */
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/** @name Clear configuration register bit definitions and masks
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* @{
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*/
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#define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE0_MASK 0x00000001 /**< Memory
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controller interface 0 interrupt disable mask */
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#define XNANDPS_MEMC_CLR_CONFIG_INT_DISABLE1_MASK 0x00000002 /**< Memory
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controller interface 1 interrupt disable mask */
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#define XNANDPS_MEMC_CLR_CONFIG_LOW_POWER_EXIT_MASK 0x00000004 /**< Memory
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controller low power exit mask */
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#define XNANDPS_MEMC_CLR_CONFIG_INT_CLR0_MASK 0x00000008 /**< Memory
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controller interface0 interrupt clear mask */
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#define XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK 0x00000010 /**< Memory
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controller interface1 interrupt clear mask */
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#define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE0_MASK 0x00000020 /**< Memory
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controller interface0 ECC interrupt disable mask */
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#define XNANDPS_MEMC_CLR_CONFIG_ECC_INT_DISABLE1_MASK 0x00000040 /**< Memory
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controller interface1 ECC interrupt disable mask */
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/* @} */
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/** @name Clear configuration register bit definitions and masks and shift
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* @{
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*/
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#define XNANDPS_DIRECT_CMD_ADDR_MASK 0x000FFFFF /**< Direct
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command address mask */
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#define XNANDPS_DIRECT_CMD_SET_CRE_MASK 0x00100000 /**< Direct
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command set cre mask */
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#define XNANDPS_DIRECT_CMD_TYPE_MASK 0x00600000 /**< Direct
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command type mask */
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#define XNANDPS_DIRECT_CMD_CHIP_SELECT_MASK 0x03800000 /**< Direct
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command chip select mask */
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#define XNANDPS_DIRECT_CMD_SET_CRE_SHIFT 20 /**< Direct command
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set_cre shift */
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#define XNANDPS_DIRECT_CMD_CMD_TYPE_SHIFT 21 /**< Direct command
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cmd_type shift */
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#define XNANDPS_DIRECT_CMD_CHIP_SELECT_SHIFT 23 /**< Direct command
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chip select shift */
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/* @} */
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/** @name Set cycles register bit definitions and masks and shift
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* @{
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*/
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#define XNANDPS_SET_CYCLES_SET_T0_MASK 0x0000000F /**< Set
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cycles set_t0 mask */
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#define XNANDPS_SET_CYCLES_SET_T1_MASK 0x000000F0 /**< Set
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cycles set_t1 mask */
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#define XNANDPS_SET_CYCLES_SET_T2_MASK 0x00000700 /**< Set
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cycles set_t2 mask */
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#define XNANDPS_SET_CYCLES_SET_T3_MASK 0x00003800 /**< Set
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cycles set_t3 mask */
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#define XNANDPS_SET_CYCLES_SET_T4_MASK 0x0001C000 /**< Set
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cycles set_t4 mask */
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#define XNANDPS_SET_CYCLES_SET_T5_MASK 0x000E0000 /**< Set
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cycles set_t5 mask */
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#define XNANDPS_SET_CYCLES_SET_T6_MASK 0x00F00000 /**< Set
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cycles set_t6 mask */
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#define XNANDPS_SET_CYCLES_SET_T0_SHIFT 0 /**< Set cycles set_t0
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shift */
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#define XNANDPS_SET_CYCLES_SET_T1_SHIFT 4 /**< Set cycles set_t1
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shift */
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#define XNANDPS_SET_CYCLES_SET_T2_SHIFT 8 /**< Set cycles set_t2
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shift */
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#define XNANDPS_SET_CYCLES_SET_T3_SHIFT 11 /**< Set cycles set_t3
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shift */
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#define XNANDPS_SET_CYCLES_SET_T4_SHIFT 14 /**< Set cycles set_t4
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shift */
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#define XNANDPS_SET_CYCLES_SET_T5_SHIFT 17 /**< Set cycles set_t5
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shift */
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#define XNANDPS_SET_CYCLES_SET_T6_SHIFT 20 /**< Set cycles set_t6
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shift */
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/* @} */
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/** @name Set opmode register bit definitions and masks
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* @{
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*/
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#define XNANDPS_SET_OPMODE_SET_MW_MASK 0x00000003 /**< Set
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opmode set memory width mask */
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#define XNANDPS_SET_OPMODE_SET_RD_SYNC_MASK 0x00000004 /**< Set
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opmode set rd_sync mask */
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#define XNANDPS_SET_OPMODE_SET_RD_BL_MASK 0x00000038 /**< Set
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opmode set rd_bl mask */
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#define XNANDPS_SET_OPMODE_SET_WR_SYNC_MASK 0x00000040 /**< Set
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opmode set wr_sync mask */
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#define XNANDPS_SET_OPMODE_SET_WR_BL_MASK 0x00000380 /**< Set
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opmode set wr_bl mask */
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#define XNANDPS_SET_OPMODE_SET_BAA_MASK 0x00000400 /**< Set
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opmode set baa mask */
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#define XNANDPS_SET_OPMODE_SET_ADV_MASK 0x00000800 /**< Set
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opmode set adv mask */
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#define XNANDPS_SET_OPMODE_SET_BLS_MASK 0x00001000 /**< Set
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opmode set bls mask */
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#define XNANDPS_SET_OPMODE_SET_BURST_ALIGN_MASK 0x0000E000 /**< Set
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opmode set burst align mask */
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#define XNANDPS_SET_OPMODE_MW_8_BITS 0x0 /**< Set opmode
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memory width value for 8-bit flash */
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#define XNANDPS_SET_OPMODE_MW_16_BITS 0x1 /**< Set opmode
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memory width value for 16-bit flash */
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#define XNANDPS_SET_OPMODE_MW_32_BITS 0x2 /**< Set opmode
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memory width value for 32-bit flash */
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/* @} */
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/** @name Refresh period register bit definitions and masks
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* @{
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*/
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#define XNANDPS_REFRESH_PERIOD_0_MASK 0x0000000F
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/**< Interface 0 refresh period mask */
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#define XNANDPS_REFRESH_PERIOD_1_MASK 0x0000000F
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/**< Interface 1 refresh period mask */
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/* @} */
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/** @name Opmode register bit definitions and masks
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* @{
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*/
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#define XNANDPS_OPMODE_MW_MASK 0x00000003
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/**< Opmode Memory width mask */
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#define XNANDPS_OPMODE_RD_SYNC_MASK 0x00000004
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/**< Opmode rd_sync mask */
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#define XNANDPS_OPMODE_RD_BL_MASK 0x00000038
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/**< Opmode rd_bl mask */
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#define XNANDPS_OPMODE_WR_SYNC_MASK 0x00000040
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/**< Opmode wr_sync mask */
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#define XNANDPS_OPMODE_WR_BL_MASK 0x00000380
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/**< Opmode BAA mask */
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#define XNANDPS_OPMODE_BAA_MASK 0x00000400
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/**< Opmode ADV mask */
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#define XNANDPS_OPMODE_ADV_MASK 0x00000800
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/**< Opmode BLS mask */
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#define XNANDPS_OPMODE_BLS_MASK 0x00001000
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/**< Opmode Burst align mask */
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#define XNANDPS_OPMODE_BURST_ALIGN_MASK 0x0000E000
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/**< Opmode Address mask */
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#define XNANDPS_OPMODE_ADDRESS_MASK 0x00FF0000
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/**< Opmode Address match mask */
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#define XNANDPS_OPMODE_ADDRESS_MATCH_MASK 0xFF000000
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/* @} */
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/** @name User status register bit definitions and masks
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* @{
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*/
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#define XNANDPS_USER_STATUS_MASK 0x000000FF /**< User
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status mask */
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/* @} */
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/** @name User config register bit definitions and masks
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* @{
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*/
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#define XNANDPS_USER_CONFIG_MASK 0x000000FF /**< User
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config mask */
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/* @} */
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/** @name ECC status register bit definitions and masks
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* @{
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*/
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#define XNANDPS_ECC_STATUS_RAW_INT_STATUS_MASK 0x0000003F /**< Ecc
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status raw_int_status mask */
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#define XNANDPS_ECC_STATUS_MASK 0x00000040 /**< Ecc
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status ecc_status mask */
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#define XNANDPS_ECC_LAST_MASK 0x00000180 /**< Ecc
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status ecc_last mask */
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#define XNANDPS_ECC_READ_NOT_WRITE_MASK 0x00000200 /**< Ecc
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status ecc_read_not_write mask */
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#define XNANDPS_ECC_VALID_MASK 0x00007C00 /**< Ecc
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status ecc_valid mask */
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#define XNANDPS_ECC_FAIL_MASK 0x000F8000 /**< Ecc
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status ecc_fail mask */
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#define XNANDPS_ECC_CAN_CORRECT_MASK 0x01F00000 /**< Ecc
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status ecc_can_correct mask */
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#define XNANDPS_ECC_READ_MASK 0x37000000 /**< Ecc
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status ecc_read mask */
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/* @} */
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/** @name ECC mem config register bit definitions and masks and shifts
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* @{
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*/
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#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_MASK 0x00000003
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/**< Ecc cfg page_size mask */
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#define XNANDPS_ECC_MEMCFG_ECC_MODE_MASK 0x0000000C
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/**< Ecc cfg ecc_mode mask */
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#define XNANDPS_ECC_MEMCFG_ECC_READ_END_MASK 0x00000010
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/**< Ecc cfg ecc_read_end mask */
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#define XNANDPS_ECC_MEMCFG_ECC_JUMP_MASK 0x00000060
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/**< Ecc cfg ecc_jump mask */
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#define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_MASK 0x00000080
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/**< Ecc cfg ecc_ignore_add_eight mask */
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#define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_MASK 0x00000100
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/**< Ecc cfg ecc_int_pass mask */
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#define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_MASK 0x00000200
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/**< Ecc cfg ecc_int_abort mask */
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#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_MASK 0x00000400
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/**< Ecc cfg ecc_extra_block mask */
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#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_MASK 0x00001800
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/**< Ecc cfg ecc_extra_block_size mask */
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#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_SHIFT 0
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/**< Ecc cfg page_size shift */
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#define XNANDPS_ECC_MEMCFG_ECC_MODE_SHIFT 2
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/**< Ecc cfg ecc_mode shift */
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#define XNANDPS_ECC_MEMCFG_ECC_READ_END_SHIFT 4
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/**< Ecc cfg ecc_read_end shift */
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#define XNANDPS_ECC_MEMCFG_ECC_JUMP_SHIFT 5
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/**< Ecc cfg ecc_jump shift */
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#define XNANDPS_ECC_MEMCFG_IGNORE_ADD8_SHIFT 7
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/**< Ecc cfg ecc_ignore_add_eight shift */
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#define XNANDPS_ECC_MEMCFG_ECC_INT_PASS_SHIFT 8
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/**< Ecc cfg ecc_int_pass shift */
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#define XNANDPS_ECC_MEMCFG_ECC_INT_ABORT_SHIFT 9
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/**< Ecc cfg ecc_int_abort shift */
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#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SHIFT 10
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/**< Ecc cfg ecc_extra_block shift */
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#define XNANDPS_ECC_MEMCFG_ECC_EXTRA_BLOCK_SIZE_SHIFT 11
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/**< Ecc cfg ecc_extra_block_size shift */
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#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_512 0x1 /**< ECC cfg
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page size value for 512 byte page */
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#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_1024 0x2 /**< ECC cfg
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page size value for 1024 byte page */
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#define XNANDPS_ECC_MEMCFG_PAGE_SIZE_2048 0x3 /**< ECC cfg
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page size value for 2048 byte page */
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/* @} */
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/* @} */
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/** @name ECC mem command1 register bit definitions and masks and shifts
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* @{
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*/
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#define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_MASK 0x000000FF
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/**< Ecc command 1 nand_wr_cmd mask */
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#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_MASK 0x0000FF00
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/**< Ecc command 1 nand_rd_cmd mask */
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#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_MASK 0x00FF0000
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/**< Ecc command 1 nand_rd_cmd_end mask */
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#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_MASK 0x01000000
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/**< Ecc command 1 nand_rd_cmd_end_valid mask */
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#define XNANDPS_ECC_MEMCOMMAND1_WR_CMD_SHIFT 0
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/**< Ecc command 1 nand_wr_cmd shift */
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#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_SHIFT 8
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/**< Ecc command 1 nand_rd_cmd shift */
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#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_SHIFT 16
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/**< Ecc command 1 nand_rd_cmd_end shift */
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#define XNANDPS_ECC_MEMCOMMAND1_RD_CMD_END_VALID_SHIFT 24
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/**< Ecc command 1 nand_rd_cmd_end_valid shift */
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|
/* @} */
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|
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/** @name ECC mem command2 register bit definitions and masks
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|
* @{
|
|
*/
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#define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_MASK 0x000000FF
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/**< Ecc command2 nand_wr_col_change mask */
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#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_MASK 0x0000FF00
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/**< Ecc command2 nand_rd_col_change mask */
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#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_MASK 0x00FF0000
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/**< Ecc command2 nand_rd_col_change_end mask */
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#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_MASK 0x00FF0000
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/**< Ecc command2 nand_rd_col_change_end_valid mask */
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|
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#define XNANDPS_ECC_MEMCOMMAND2_WR_COL_CHANGE_SHIFT 0
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/**< Ecc command2 nand_wr_col_change shift */
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#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_SHIFT 8
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|
/**< Ecc command2 nand_rd_col_change shift */
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|
#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_SHIFT 16
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|
/**< Ecc command2 nand_rd_col_change_end shift */
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|
#define XNANDPS_ECC_MEMCOMMAND2_RD_COL_CHANGE_END_VALID_SHIFT 24
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|
/**< Ecc command2 nand_rd_col_change_end_valid shift */
|
|
/* @} */
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|
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|
/** @name ECC value register bit definitions and masks
|
|
* @{
|
|
*/
|
|
#define XNANDPS_ECC_VALUE_MASK 0x00FFFFFF
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|
/**< Ecc value ecc_value mask */
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|
#define XNANDPS_ECC_VALUE_CORRECT_MASK 0x08000000
|
|
/**< Ecc value ecc_correct mask */
|
|
#define XNANDPS_ECC_VALUE_FAIL_MASK 0x10000000
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|
/**< Ecc value ecc_fail mask */
|
|
#define XNANDPS_ECC_VALUE_READ_MASK 0x20000000
|
|
/**< Ecc value ecc_read mask */
|
|
#define XNANDPS_ECC_VALUE_VALID_MASK 0x40000000
|
|
/**< Ecc value ecc_valid mask */
|
|
#define XNANDPS_ECC_VALUE_INT_MASK 0x80000000
|
|
/**< Ecc value ecc_int mask */
|
|
/* @} */
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|
|
|
/** @name Peripheral ID register bit definitions and masks
|
|
* @{
|
|
*/
|
|
#define XNANDPS_PERIPH_ID_PART_NUM_MASK 0x00000FFF
|
|
/**< Peripheral ID part_num mask */
|
|
#define XNANDPS_PERIPH_ID_DESIGNER_ID_MASK 0x000FF000
|
|
/**< Peripheral ID designed id mask */
|
|
#define XNANDPS_PERIPH_ID_REVISION_MASK 0x00F00000
|
|
/**< Peripheral ID revision mask */
|
|
#define XNANDPS_PERIPH_ID_INTG_CFG_MASK 0x01000000
|
|
/**< Peripheral ID integration_cfg mask */
|
|
/* @} */
|
|
|
|
/** @name Peripheral ID register bit definitions and masks
|
|
* @{
|
|
*/
|
|
#define XNANDPS_PCELL_ID_MASK 0x000000FF
|
|
/**< Primecell identification register mask */
|
|
/* @} */
|
|
|
|
/**************************** Type Definitions *******************************/
|
|
|
|
/***************** Macros (Inline Functions) Definitions *********************/
|
|
#define XNandPs_ReadReg Xil_In32 /**< XNandPs Register register */
|
|
#define XNandPs_WriteReg Xil_Out32 /**< XNandPs register write */
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
|
|
/************************** Variable Definitions *****************************/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* end of protection macro */
|