86241705f9
Added source files,example files, Modified .tcl file. Signed-off-by: Durga challa <vnsldurg@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
552 lines
21 KiB
C
Executable file
552 lines
21 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xcresample_hw.h
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*
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* This header file contains identifiers and register-level driver functions
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* (or macros) that can be used to access the Xilinx Chroma Resampler core.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------- -------- -------------------------------------------------------
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* 4.0 adk 03/12/14 First release
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* Added the register offsets and bit masks for the
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* registers and added backward compatibility for macros.
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XCRESAMPLE_HW_H_
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#define XCRESAMPLE_HW_H_ /**< Prevent circular inclusions
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* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name register offsets
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* @{
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*/
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/* General control registers */
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#define XCRE_CONTROL_OFFSET 0x0000 /**< Control */
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#define XCRE_STATUS_OFFSET 0x0004 /**< Status */
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#define XCRE_ERROR_OFFSET 0x0008 /**< Error */
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#define XCRE_IRQ_EN_OFFSET 0x000C /**< IRQ enable */
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#define XCRE_VERSION_OFFSET 0x0010 /**< Version */
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#define XCRE_SYSDEBUG0_OFFSET 0x0014 /**< System debug 0 */
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#define XCRE_SYSDEBUG1_OFFSET 0x0018 /**< System debug 1 */
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#define XCRE_SYSDEBUG2_OFFSET 0x001C /**< System debug 2 */
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/*@}*/
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/* Timing control registers */
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#define XCRE_ACTIVE_SIZE_OFFSET 0x0020 /**< Horizontal and vertical
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* active frame size */
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#define XCRE_ENCODING_OFFSET 0x0028 /**< Frame encoding */
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/* Core specific registers */
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/* Coefficient Registers for Horizontal Filter Phase 0 */
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#define XCRE_COEF00_HPHASE0_OFFSET 0x0100 /**< Coefficient 00 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF01_HPHASE0_OFFSET 0x0104 /**< Coefficient 01 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF02_HPHASE0_OFFSET 0x0108 /**< Coefficient 02 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF03_HPHASE0_OFFSET 0x010C /**< Coefficient 03 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF04_HPHASE0_OFFSET 0x0110 /**< Coefficient 04 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF05_HPHASE0_OFFSET 0x0114 /**< Coefficient 05 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF06_HPHASE0_OFFSET 0x0118 /**< Coefficient 06 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF07_HPHASE0_OFFSET 0x011C /**< Coefficient 07 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF08_HPHASE0_OFFSET 0x0120 /**< Coefficient 08 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF09_HPHASE0_OFFSET 0x0124 /**< Coefficient 09 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF10_HPHASE0_OFFSET 0x0128 /**< Coefficient 10 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF11_HPHASE0_OFFSET 0x012C /**< Coefficient 11 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF12_HPHASE0_OFFSET 0x0130 /**< Coefficient 12 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF13_HPHASE0_OFFSET 0x0134 /**< Coefficient 13 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF14_HPHASE0_OFFSET 0x0138 /**< Coefficient 14 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF15_HPHASE0_OFFSET 0x013C /**< Coefficient 15 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF16_HPHASE0_OFFSET 0x0140 /**< Coefficient 16 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF17_HPHASE0_OFFSET 0x0144 /**< Coefficient 17 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF18_HPHASE0_OFFSET 0x0148 /**< Coefficient 18 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF19_HPHASE0_OFFSET 0x014C /**< Coefficient 19 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF20_HPHASE0_OFFSET 0x0150 /**< Coefficient 20 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF21_HPHASE0_OFFSET 0x0154 /**< Coefficient 21 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF22_HPHASE0_OFFSET 0x0158 /**< Coefficient 22 of
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* horizontal phase 0
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* filter */
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#define XCRE_COEF23_HPHASE0_OFFSET 0x015C /**< Coefficient 23 of
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* horizontal phase 0
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* filter */
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/* Coefficient Registers for Horizontal Filter Phase 1 */
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#define XCRE_COEF00_HPHASE1_OFFSET 0x0160 /**< Coefficient 00 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF01_HPHASE1_OFFSET 0x0164 /**< Coefficient 01 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF02_HPHASE1_OFFSET 0x0168 /**< Coefficient 02 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF03_HPHASE1_OFFSET 0x016C /**< Coefficient 03 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF04_HPHASE1_OFFSET 0x0170 /**< Coefficient 04 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF05_HPHASE1_OFFSET 0x0174 /**< Coefficient 05 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF06_HPHASE1_OFFSET 0x0178 /**< Coefficient 06 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF07_HPHASE1_OFFSET 0x017C /**< Coefficient 07 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF08_HPHASE1_OFFSET 0x0180 /**< Coefficient 08 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF09_HPHASE1_OFFSET 0x0184 /**< Coefficient 09 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF10_HPHASE1_OFFSET 0x0188 /**< Coefficient 10 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF11_HPHASE1_OFFSET 0x018C /**< Coefficient 11 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF12_HPHASE1_OFFSET 0x0190 /**< Coefficient 12 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF13_HPHASE1_OFFSET 0x0194 /**< Coefficient 13 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF14_HPHASE1_OFFSET 0x0198 /**< Coefficient 14 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF15_HPHASE1_OFFSET 0x019C /**< Coefficient 15 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF16_HPHASE1_OFFSET 0x01A0 /**< Coefficient 16 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF17_HPHASE1_OFFSET 0x01A4 /**< Coefficient 17 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF18_HPHASE1_OFFSET 0x01A8 /**< Coefficient 18 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF19_HPHASE1_OFFSET 0x01AC /**< Coefficient 19 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF20_HPHASE1_OFFSET 0x01B0 /**< Coefficient 20 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF21_HPHASE1_OFFSET 0x01B4 /**< Coefficient 21 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF22_HPHASE1_OFFSET 0x01B8 /**< Coefficient 22 of
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* horizontal phase 1
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* filter */
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#define XCRE_COEF23_HPHASE1_OFFSET 0x01BC /**< Coefficient 23 of
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* horizontal phase 1
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* filter */
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/* Coefficient Registers for Vertical Filter Phase 0 */
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#define XCRE_COEF00_VPHASE0_OFFSET 0x01C0 /**< Coefficient 00 of
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* vertical phase 0
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* filter */
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#define XCRE_COEF01_VPHASE0_OFFSET 0x01C4 /**< Coefficient 01 of
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* vertical phase 0
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* filter */
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#define XCRE_COEF02_VPHASE0_OFFSET 0x01C8 /**< Coefficient 02 of
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* vertical phase 0
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* filter */
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#define XCRE_COEF03_VPHASE0_OFFSET 0x01CC /**< Coefficient 03 of
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* vertical phase 0
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* filter */
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#define XCRE_COEF04_VPHASE0_OFFSET 0x01D0 /**< Coefficient 04 of
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* vertical phase 0
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* filter */
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#define XCRE_COEF05_VPHASE0_OFFSET 0x01D4 /**< Coefficient 05 of
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* vertical phase 0
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* filter */
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#define XCRE_COEF06_VPHASE0_OFFSET 0x01D8 /**< Coefficient 06 of
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* vertical phase 0
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* filter */
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#define XCRE_COEF07_VPHASE0_OFFSET 0x01DC /**< Coefficient 07 of
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* vertical phase 0
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* filter */
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/* Coefficient Registers for Vertical Filter Phase 1 */
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#define XCRE_COEF00_VPHASE1_OFFSET 0x01E0 /**< Coefficient 00 of
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* vertical phase 1
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* filter */
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#define XCRE_COEF01_VPHASE1_OFFSET 0x01E4 /**< Coefficient 01 of
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* vertical phase 1
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* filter */
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#define XCRE_COEF02_VPHASE1_OFFSET 0x01E8 /**< Coefficient 02 of
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* vertical phase 1
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* filter */
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#define XCRE_COEF03_VPHASE1_OFFSET 0x01EC /**< Coefficient 03 of
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* vertical phase 1
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* filter */
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#define XCRE_COEF04_VPHASE1_OFFSET 0x01F0 /**< Coefficient 04 of
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* vertical phase 1
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* filter */
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#define XCRE_COEF05_VPHASE1_OFFSET 0x01F4 /**< Coefficient 05 of
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* vertical phase 1
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* filter */
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#define XCRE_COEF06_VPHASE1_OFFSET 0x01F8 /**< Coefficient 06 of
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* vertical phase 1
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* filter */
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#define XCRE_COEF07_VPHASE1_OFFSET 0x01FC /**< Coefficient 07 of
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* vertical phase 1
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* filter */
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/*@}*/
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/** @name Control register bit masks
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* @{
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*/
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#define XCRE_CTL_SW_EN_MASK 0x00000001 /**< Enable mask */
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#define XCRE_CTL_RUE_MASK 0x00000002 /**< Register update mask */
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#define XCRE_CTL_BPE_MASK 0x00000010 /**< Bypass mask */
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#define XCRE_CTL_TPE_MASK 0x00000020 /**< Test pattern mask */
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#define XCRE_CTL_AUTORESET_MASK 0x40000000 /**< Software reset -
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* Auto-synchronize to SOF
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* mask */
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#define XCRE_CTL_RESET_MASK 0x80000000 /**< Software reset -
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* instantaneous mask */
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/*@}*/
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/** @name Interrupt register bit masks. It is applicable for
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* Status and IRQ_ENABLE Registers
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* @{
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*/
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#define XCRE_IXR_PROCS_STARTED_MASK 0x00000001 /**< Proc started mask */
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#define XCRE_IXR_EOF_MASK 0x00000002 /**< End-Of-Frame mask */
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#define XCRE_IXR_SE_MASK 0x00010000 /**< Slave Error mask */
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#define XCRE_IXR_ALLINTR_MASK 0x00010003U /**< OR of all mask */
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/* ((XCRE_IXR_PROCS_MASK) | (XCRE_IXR_EOF_MASK) | \
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* (XCRE_IXR_SE_MASK)) */
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/*@}*/
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/** @name Error register bit masks
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* @{
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*/
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#define XCRE_ERR_EOL_EARLY_MASK 0x00000001 /**< Error: End of Line
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* Early mask */
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#define XCRE_ERR_EOL_LATE_MASK 0x00000002 /**< Error: End of Line
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* Late mask */
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#define XCRE_ERR_SOF_EARLY_MASK 0x00000004 /**< Error: Start of
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* Frame Early mask */
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#define XCRE_ERR_SOF_LATE_MASK 0x00000008 /**< Error: Start of
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* Frame Late mask */
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/*@}*/
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/** @name Version register bit masks and shifts
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* @{
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*/
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#define XCRE_VER_REV_NUM_MASK 0x000000FF /**< Revision Number mask */
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#define XCRE_VER_PID_MASK 0x00000F00 /**< Patch ID mask */
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#define XCRE_VER_REV_MASK 0x0000F000 /**< Version Revision mask */
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#define XCRE_VER_MINOR_MASK 0x00FF0000 /**< Version Minor mask */
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#define XCRE_VER_MAJOR_MASK 0xFF000000 /**< Version Major mask */
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#define XCRE_VER_INTERNAL_SHIFT 0x00000008 /**< Patch ID shift */
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#define XCRE_VER_REV_SHIFT 0x0000000C /**< Version Revision shift */
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#define XCRE_VER_MINOR_SHIFT 0x00000010 /**< Version Minor shift */
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#define XCRE_VER_MAJOR_SHIFT 0x00000018 /**< Version Major shift */
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/*@}*/
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/** @name Active size register bit masks and shifts
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* @{
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*/
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#define XCRE_ACTSIZE_NUM_PIXEL_MASK 0x00001FFF /**< Number of Active pixels
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* per scan line (horizontal)
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* mask */
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#define XCRE_ACTSIZE_NUM_LINE_MASK 0x1FFF0000 /**< Number of Active lines per
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* frame (Vertical) mask */
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#define XCRE_ACTSIZE_NUM_LINE_SHIFT 16 /**< Shift for number of
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* lines */
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/*@}*/
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/** @name Encoding register bit masks and shifts
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* @{
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*/
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#define XCRE_ENCODING_FIELD_MASK 0x00000080 /**< Field parity mask */
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#define XCRE_ENCODING_CHROMA_MASK 0x00000100 /**< Chroma parity mask */
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#define XCRE_ENCODING_FIELD_SHIFT 7 /**< Field parity shift */
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#define XCRE_ENCODING_CHROMA_SHIFT 8 /**< Chroma parity shift */
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/*@}*/
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/** @name Coefficient bit mask and shift
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* @{
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*/
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#define XCRE_COEFF_FRAC_MASK 0x00003FFF /**< Mask of Fractional part */
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#define XCRE_COEF_DECI_MASK 0x00004000 /**< Mask of Decimal part */
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#define XCRE_COEF_SIGN_MASK 0x00008000 /**< Mask for Coefficient sign
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* bit */
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#define XCRE_COEFF_MASK 0x0000FFFF /**< Coefficient mask */
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#define XCRE_COEFF_SHIFT 14 /**< Shift for decimal value */
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#define XCRE_COEFF_SIGN_SHIFT 16 /**< Coefficient shift */
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/*@}*/
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/** @name General purpose macros
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* @{
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*/
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#define XCRE_SIGN_MUL -1 /**< Macro for sign
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* multiplication */
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#define XCRE_SIGNBIT_MASK 0x10000000 /** Mask for sign bit of 32
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* bit number */
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#define XCRE_MAX_VALUE 0xFFFFFFFF /**< 32 bit maximum value */
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/*@}*/
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/** @name backward compatibility macros
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*
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* To support backward compatibility following macro definition are
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* re-defined.
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* @{
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*/
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#define CRESAMPLE_CONTROL XCRE_CONTROL_OFFSET
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#define CRESAMPLE_STATUS XCRE_STATUS_OFFSET
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#define CRESAMPLE_ERROR XCRE_ERROR_OFFSET
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#define CRESAMPLE_IRQ_ENABLE XCRE_IRQ_EN_OFFSET
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#define CRESAMPLE_VERSION XCRE_VERSION_OFFSET
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#define CRESAMPLE_SYSDEBUG0 XCRE_SYSDEBUG0_OFFSET
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#define CRESAMPLE_SYSDEBUG1 XCRE_SYSDEBUG1_OFFSET
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#define CRESAMPLE_SYSDEBUG2 XCRE_SYSDEBUG2_OFFSET
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#define CRESAMPLE_ACTIVE_SIZE XCRE_ACTIVE_SIZE_OFFSET
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#define CRESAMPLE_ENCODING XCRE_ENCODING_OFFSET
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#define CRESAMPLE_COEF00_HPHASE0 XCRE_COEF00_HPHASE0_OFFSET
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#define CRESAMPLE_COEF01_HPHASE0 XCRE_COEF01_HPHASE0_OFFSET
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#define CRESAMPLE_COEF02_HPHASE0 XCRE_COEF02_HPHASE0_OFFSET
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#define CRESAMPLE_COEF03_HPHASE0 XCRE_COEF03_HPHASE0_OFFSET
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#define CRESAMPLE_COEF04_HPHASE0 XCRE_COEF04_HPHASE0_OFFSET
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#define CRESAMPLE_COEF05_HPHASE0 XCRE_COEF05_HPHASE0_OFFSET
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#define CRESAMPLE_COEF06_HPHASE0 XCRE_COEF06_HPHASE0_OFFSET
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#define CRESAMPLE_COEF07_HPHASE0 XCRE_COEF07_HPHASE0_OFFSET
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#define CRESAMPLE_COEF08_HPHASE0 XCRE_COEF08_HPHASE0_OFFSET
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#define CRESAMPLE_COEF09_HPHASE0 XCRE_COEF09_HPHASE0_OFFSET
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#define CRESAMPLE_COEF10_HPHASE0 XCRE_COEF10_HPHASE0_OFFSET
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#define CRESAMPLE_COEF11_HPHASE0 XCRE_COEF11_HPHASE0_OFFSET
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#define CRESAMPLE_COEF12_HPHASE0 XCRE_COEF12_HPHASE0_OFFSET
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#define CRESAMPLE_COEF13_HPHASE0 XCRE_COEF13_HPHASE0_OFFSET
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#define CRESAMPLE_COEF14_HPHASE0 XCRE_COEF14_HPHASE0_OFFSET
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#define CRESAMPLE_COEF15_HPHASE0 XCRE_COEF15_HPHASE0_OFFSET
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#define CRESAMPLE_COEF16_HPHASE0 XCRE_COEF16_HPHASE0_OFFSET
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#define CRESAMPLE_COEF17_HPHASE0 XCRE_COEF17_HPHASE0_OFFSET
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#define CRESAMPLE_COEF18_HPHASE0 XCRE_COEF18_HPHASE0_OFFSET
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#define CRESAMPLE_COEF19_HPHASE0 XCRE_COEF19_HPHASE0_OFFSET
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#define CRESAMPLE_COEF20_HPHASE0 XCRE_COEF20_HPHASE0_OFFSET
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#define CRESAMPLE_COEF21_HPHASE0 XCRE_COEF21_HPHASE0_OFFSET
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#define CRESAMPLE_COEF22_HPHASE0 XCRE_COEF22_HPHASE0_OFFSET
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#define CRESAMPLE_COEF23_HPHASE0 XCRE_COEF23_HPHASE0_OFFSET
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#define CRESAMPLE_COEF00_HPHASE1 XCRE_COEF00_HPHASE1_OFFSET
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#define CRESAMPLE_COEF01_HPHASE1 XCRE_COEF01_HPHASE1_OFFSET
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#define CRESAMPLE_COEF02_HPHASE1 XCRE_COEF02_HPHASE1_OFFSET
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#define CRESAMPLE_COEF03_HPHASE1 XCRE_COEF03_HPHASE1_OFFSET
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#define CRESAMPLE_COEF04_HPHASE1 XCRE_COEF04_HPHASE1_OFFSET
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#define CRESAMPLE_COEF05_HPHASE1 XCRE_COEF05_HPHASE1_OFFSET
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#define CRESAMPLE_COEF06_HPHASE1 XCRE_COEF06_HPHASE1_OFFSET
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#define CRESAMPLE_COEF07_HPHASE1 XCRE_COEF07_HPHASE1_OFFSET
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#define CRESAMPLE_COEF08_HPHASE1 XCRE_COEF08_HPHASE1_OFFSET
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#define CRESAMPLE_COEF09_HPHASE1 XCRE_COEF09_HPHASE1_OFFSET
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#define CRESAMPLE_COEF10_HPHASE1 XCRE_COEF10_HPHASE1_OFFSET
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#define CRESAMPLE_COEF11_HPHASE1 XCRE_COEF11_HPHASE1_OFFSET
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#define CRESAMPLE_COEF12_HPHASE1 XCRE_COEF12_HPHASE1_OFFSET
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#define CRESAMPLE_COEF13_HPHASE1 XCRE_COEF13_HPHASE1_OFFSET
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#define CRESAMPLE_COEF14_HPHASE1 XCRE_COEF14_HPHASE1_OFFSET
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#define CRESAMPLE_COEF15_HPHASE1 XCRE_COEF15_HPHASE1_OFFSET
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#define CRESAMPLE_COEF16_HPHASE1 XCRE_COEF16_HPHASE1_OFFSET
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#define CRESAMPLE_COEF17_HPHASE1 XCRE_COEF17_HPHASE1_OFFSET
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#define CRESAMPLE_COEF18_HPHASE1 XCRE_COEF18_HPHASE1_OFFSET
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#define CRESAMPLE_COEF19_HPHASE1 XCRE_COEF19_HPHASE1_OFFSET
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#define CRESAMPLE_COEF20_HPHASE1 XCRE_COEF20_HPHASE1_OFFSET
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#define CRESAMPLE_COEF21_HPHASE1 XCRE_COEF21_HPHASE1_OFFSET
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#define CRESAMPLE_COEF22_HPHASE1 XCRE_COEF22_HPHASE1_OFFSET
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#define CRESAMPLE_COEF23_HPHASE1 XCRE_COEF23_HPHASE1_OFFSET
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#define CRESAMPLE_COEF00_VPHASE0 XCRE_COEF00_VPHASE0_OFFSET
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#define CRESAMPLE_COEF01_VPHASE0 XCRE_COEF01_VPHASE0_OFFSET
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#define CRESAMPLE_COEF02_VPHASE0 XCRE_COEF02_VPHASE0_OFFSET
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#define CRESAMPLE_COEF03_VPHASE0 XCRE_COEF03_VPHASE0_OFFSET
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#define CRESAMPLE_COEF04_VPHASE0 XCRE_COEF04_VPHASE0_OFFSET
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#define CRESAMPLE_COEF05_VPHASE0 XCRE_COEF05_VPHASE0_OFFSET
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#define CRESAMPLE_COEF06_VPHASE0 XCRE_COEF06_VPHASE0_OFFSET
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#define CRESAMPLE_COEF07_VPHASE0 XCRE_COEF07_VPHASE0_OFFSET
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#define CRESAMPLE_COEF00_VPHASE1 XCRE_COEF00_VPHASE1_OFFSET
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#define CRESAMPLE_COEF01_VPHASE1 XCRE_COEF01_VPHASE1_OFFSET
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#define CRESAMPLE_COEF02_VPHASE1 XCRE_COEF02_VPHASE1_OFFSET
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#define CRESAMPLE_COEF03_VPHASE1 XCRE_COEF03_VPHASE1_OFFSET
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#define CRESAMPLE_COEF04_VPHASE1 XCRE_COEF04_VPHASE1_OFFSET
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#define CRESAMPLE_COEF05_VPHASE1 XCRE_COEF05_VPHASE1_OFFSET
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#define CRESAMPLE_COEF06_VPHASE1 XCRE_COEF06_VPHASE1_OFFSET
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#define CRESAMPLE_COEF07_VPHASE1 XCRE_COEF07_VPHASE1_OFFSET
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#define CRESAMPLE_CTL_EN_MASK XCRE_CTL_SW_EN_MASK
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#define CRESAMPLE_CTL_RU_MASK XCRE_CTL_RUE_MASK
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#define CRESAMPLE_CTL_AUTORESET XCRE_CTL_AUTORESET_MASK
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#define CRESAMPLE_CTL_RESET XCRE_CTL_RESET_MASK
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#define CRESAMPLE_In32 XCresample_In32
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#define CRESAMPLE_Out32 XCresample_Out32
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#define CRESAMPLE_ReadReg XCresample_ReadReg
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#define CRESAMPLE_WriteReg XCresample_WriteReg
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/*@}*/
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/** @name Interrupt registers
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* @{
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*/
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#define XCRE_ISR_OFFSET XCRE_STATUS_OFFSET /**< Interrupt status
|
|
* register */
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#define XCRE_IER_OFFSET XCRE_IRQ_EN_OFFSET /**< Interrupt enable
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|
.*..register
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* corresponds to
|
|
* status bits */
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/*@}*/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XCresample_In32 Xil_In32 /**< Input operations */
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#define XCresample_Out32 Xil_Out32 /**< Output operations */
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/*****************************************************************************/
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/**
|
|
*
|
|
* This macro reads the given register.
|
|
*
|
|
* @param BaseAddress is the Xilinx base address of the Chroma
|
|
* Resampler core
|
|
* @param RegOffset is the register offset of the register (defined at
|
|
* top of this file)
|
|
*
|
|
* @return The 32-bit value of the register
|
|
*
|
|
* @note C-style signature:
|
|
* u32 XCresample_ReadReg(u32 BaseAddress, u32 RegOffset)
|
|
*
|
|
******************************************************************************/
|
|
#define XCresample_ReadReg(BaseAddress, RegOffset) \
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|
XCresample_In32((BaseAddress) + (u32)(RegOffset))
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|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This macro writes into the given register.
|
|
*
|
|
* @param BaseAddress is the Xilinx base address of the Chroma
|
|
* Resampler core
|
|
* @param RegOffset is the register offset of the register
|
|
* (defined at top of this file)
|
|
* @param Data is the 32-bit value to write to the register
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note C-style signature:
|
|
* void XCresample_WriteReg(u32 BaseAddress, u32 RegOffset,
|
|
* u32 Data)
|
|
*
|
|
******************************************************************************/
|
|
#define XCresample_WriteReg(BaseAddress, RegOffset, Data) \
|
|
XCresample_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
|
|
|
|
/**************************** Type Definitions *******************************/
|
|
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
|
|
|
|
/************************** Variable Declarations ****************************/
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
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|
#endif
|
|
#endif /* End of protection macro */
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