2a550bf65e
This patch updates the doxygen for the drivers trafgen,ttcps,uartlite,uartns550,uartps to include .h files in the listof files provided in the index.html file. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
108 lines
6.2 KiB
HTML
Executable file
108 lines
6.2 KiB
HTML
Executable file
<html>
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<head>
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<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
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<title>
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Xilinx Driver uartps v2_2: uartps v2_2
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</title>
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<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
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</head>
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<hl>Software Drivers</hl>
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<hr class="whs1">
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<!-- Generated by Doxygen 1.6.1 -->
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<div class="navigation" id="top">
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<div class="tabs">
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<ul>
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<li class="current"><a href="index.html"><span>Main Page</span></a></li>
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<li><a href="annotated.html"><span>Classes</span></a></li>
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<li><a href="files.html"><span>Files</span></a></li>
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</ul>
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</div>
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</div>
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<div class="contents">
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<h1>uartps v2_2</h1><p>This driver supports the following features:</p>
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<ul>
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<li>Dynamic data format (baud rate, data bits, stop bits, parity)</li>
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<li>Polled mode</li>
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<li>Interrupt driven mode</li>
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<li>Transmit and receive FIFOs (32 byte FIFO depth)</li>
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<li>Access to the external modem control lines</li>
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</ul>
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<p><b>Initialization & Configuration</b></p>
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<p>The <a class="el" href="struct_x_uart_ps___config.html">XUartPs_Config</a> structure is used by the driver to configure itself. Fields inside this structure are properties of <a class="el" href="struct_x_uart_ps.html">XUartPs</a> based on its hardware build.</p>
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<p>To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized in the following way:</p>
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<ul>
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<li>XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a configuration structure provided by the caller. If running in a system with address translation, the parameter EffectiveAddr should be the virtual address.</li>
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</ul>
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<p><b>Baud Rate</b></p>
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<p>The UART has an internal baud rate generator, which furnishes the baud rate clock for both the receiver and the transmitter. Ther input clock frequency can be either the master clock or the master clock divided by 8, configured through the mode register.</p>
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<p>Accompanied with the baud rate divider register, the baud rate is determined by: </p>
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<pre>
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baud_rate = input_clock / (bgen * (bdiv + 1)
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</pre><p> where bgen is the value of the baud rate generator, and bdiv is the value of baud rate divider.</p>
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<p><b>Interrupts</b></p>
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<p>The FIFOs are not flushed when the driver is initialized, but a function is provided to allow the user to reset the FIFOs if desired.</p>
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<p>The driver defaults to no interrupts at initialization such that interrupts must be enabled if desired. An interrupt is generated for one of the following conditions.</p>
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<ul>
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<li>A change in the modem signals</li>
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<li>Data in the receive FIFO for a configuable time without receiver activity</li>
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<li>A parity error</li>
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<li>A framing error</li>
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<li>An overrun error</li>
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<li>Transmit FIFO is full</li>
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<li>Transmit FIFO is empty</li>
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<li>Receive FIFO is full</li>
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<li>Receive FIFO is empty</li>
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<li>Data in the receive FIFO equal to the receive threshold</li>
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</ul>
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<p>The application can control which interrupts are enabled using the <a class="el" href="xuartps_8h.html#ab3b65e926f6f4ac7ab41a70801ba12c3">XUartPs_SetInterruptMask()</a> function.</p>
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<p>In order to use interrupts, it is necessary for the user to connect the driver interrupt handler, <a class="el" href="xuartps_8h.html#abf86fb20a58e4a7fbd73afa49f8eb604">XUartPs_InterruptHandler()</a>, to the interrupt system of the application. A separate handler should be provided by the application to communicate with the interrupt system, and conduct application specific interrupt handling. An application registers its own handler through the <a class="el" href="xuartps_8h.html#a9528098e589491997c7805592a4b5a7b">XUartPs_SetHandler()</a> function.</p>
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<p><b>Data Transfer</b></p>
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<p>The functions, <a class="el" href="xuartps_8c.html#adff739cf6e252c42a050e92d3a265172">XUartPs_Send()</a> and <a class="el" href="xuartps_8c.html#a74e1aeb2b28a79a9e17e431280296a60">XUartPs_Recv()</a>, are provided in the driver to allow data to be sent and received. They can be used in either polled or interrupt mode.</p>
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<dl class="note"><dt><b>Note:</b></dt><dd></dd></dl>
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<p>The default configuration for the UART after initialization is:</p>
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<ul>
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<li>9,600 bps or XPAR_DFT_BAUDRATE if defined</li>
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<li>8 data bits</li>
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<li>1 stop bit</li>
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<li>no parity</li>
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<li>FIFO's are enabled with a receive threshold of 8 bytes</li>
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<li>The RX timeout is enabled with a timeout of 1 (4 char times)</li>
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</ul>
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<pre>
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MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
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----- ------ -------- ----------------------------------------------
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1.00a drg/jz 01/12/10 First Release
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1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
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in XUartPs_SetFlowDelay where the value was not
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being written to the register.
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1.01a sdm 12/20/11 Removed the InputClockHz parameter from the <a class="el" href="struct_x_uart_ps.html">XUartPs</a>
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instance structure and the driver is updated to use
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InputClockHz parameter from the <a class="el" href="struct_x_uart_ps___config.html">XUartPs_Config</a> config
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structure.
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Added a parameter to <a class="el" href="struct_x_uart_ps___config.html">XUartPs_Config</a> structure which
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specifies whether the user has selected Modem pins
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to be connected to MIO or FMIO.
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Added the tcl file to generate the xparameters.h
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1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
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1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
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with the correct values for CR 666724
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Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
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and XUARTPS_IXR_TTRIG.
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Modified the name of these defines
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XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
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XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
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XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
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XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
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1.05a hk 08/22/13 Added API for uart reset and related
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constant definitions.
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2.0 hk 03/07/14 Version number revised.
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2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
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2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
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baud rate. CR# 804281.</pre><pre> </pre> </div>
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<p class="Copyright">
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Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
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</p>
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</body>
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