7ca1fb1844
Example has been modified to support both Zynq PL eFuse and Ultrascale eFuse. Added GPIO pins and channels to access Master Jtag through GPIO and RSA key hash, AES's CRC value input macros are also added. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Reviewed-by: Harini Katakam <harinik@xilinx.com> |
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