2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
150 lines
5.6 KiB
C
Executable file
150 lines
5.6 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xgpiops_hw.h
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*
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* This header file contains the identifiers and basic driver functions (or
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* macros) that can be used to access the device. Other driver functions
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* are defined in xgpiops.h.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------
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* 1.00a sv 01/15/10 First Release
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* 1.02a hk 08/22/13 Added low level reset API function prototype and
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* related constant definitions
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* </pre>
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*
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******************************************************************************/
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#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
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#define XGPIOPS_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/***************************** Include Files *********************************/
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Register offsets for the GPIO. Each register is 32 bits.
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* @{
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*/
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#define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */
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#define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */
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#define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */
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#define XGPIOPS_DATA_RO_OFFSET 0x060 /* Data Register - Input, RO */
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#define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */
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#define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */
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#define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */
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#define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */
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#define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/
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#define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */
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#define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */
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#define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */
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#define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */
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/* @} */
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/** @name Register offsets for each Bank.
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* @{
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*/
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#define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */
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#define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */
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#define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */
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/* @} */
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/* For backwards compatibility */
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#define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET
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/** @name Interrupt type reset values for each bank
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* @{
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*/
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#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF
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#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF
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#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF
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#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF
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/* @} */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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/**
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*
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* This macro reads the given register.
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*
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* @param BaseAddr is the base address of the device.
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* @param RegOffset is the register offset to be read.
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*
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* @return The 32-bit value of the register
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*
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* @note None.
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*
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*****************************************************************************/
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#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
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Xil_In32((BaseAddr) + (RegOffset))
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/****************************************************************************/
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/**
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*
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* This macro writes to the given register.
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*
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* @param BaseAddr is the base address of the device.
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* @param RegOffset is the offset of the register to be written.
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* @param Data is the 32-bit value to write to the register.
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*
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* @return None.
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*
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* @note None.
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*
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*****************************************************************************/
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#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
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Xil_Out32((BaseAddr) + (RegOffset), (Data))
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/************************** Function Prototypes ******************************/
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void XGpioPs_ResetHw(u32 BaseAddress);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* XGPIOPS_HW_H */
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