Subbaraya Sundeep Bhatta a3ef256b4f spi: Use interrupt status register Tx empty bit ... Use interrupt status register Tx empty bit instead of status register Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com> Acked-by: Kedareswara rao Appana <appanad@xilinx.com>		2014-09-02 11:21:17 +05:30
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data	Renaming of common TCL procs of HSM	2014-09-02 11:20:54 +05:30
doc/html/api	embeddesw: Add initial code support	2014-06-24 16:45:01 +05:30
examples	embeddesw: Add initial code support	2014-06-24 16:45:01 +05:30
src	spi: Use interrupt status register Tx empty bit	2014-09-02 11:21:17 +05:30