485 lines
14 KiB
C
Executable file
485 lines
14 KiB
C
Executable file
/****************************************************************************
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*
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* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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* and (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage
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* of any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought by
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* a third party) even if such damage or loss was reasonably foreseeable or
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* Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or
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* environmental damage (individually and collectively, "Critical
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* Applications"). Customer assumes the sole risk and liability of any use of
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* Xilinx products in Critical Applications, subject only to applicable laws
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* and regulations governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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*****************************************************************************/
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/****************************************************************************/
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/**
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* @file xaxipcie_rc_enumerate_example.c
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*
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* This file contains a design example for using AXI PCIe IP and its driver.
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* This is an example to show the usage of driver APIs when AXI PCIe IP is
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* configured as a Root Port. The AXI PCIe can be configured as a Root Port
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* only on the 7 Series Xilinx FPGA families.
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*
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* The example initialises the AXI PCIe IP and shows how to enumerate the PCIe
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* system.
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*
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* @note
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*
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* This example should be used only when AXI PCIe IP is configured as
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* root complex.
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*
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* This code will illustrate how the XAxiPcie IP and its standalone driver can
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* be used to:
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* - Initialize a AXI PCIe IP core built as a root complex
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* - Enumerate PCIe end points in the system
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*
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* Please note that this example enumerates and initializes PCIe end points
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* only. It does not shows how to deal with PCIe switches (and its virtual
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* P2P bridges)
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*
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* We tried to use as much of the driver's API calls as possible to show the
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* reader how each call could be used and that probably made the example not
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* the shortest way of doing the tasks shown as they could be done.
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*
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*<pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 2.00a nm 10/19/11 Initial version of AXI PCIe root complex example
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* 2.02a nm 08/19/12 Removed the calls to XAxiPcie_GetLocalBusBar2PcieBar
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* and XAxiPcie_SetLocalBusBar2PcieBar as they are not
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* needed for enumeration
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*
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*</pre>
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*****************************************************************************/
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/***************************** Include Files ********************************/
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#include "xparameters.h" /* Defines for XPAR constants */
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#include "xaxipcie.h" /* XAxiPcie level 1 interface */
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#include "stdio.h"
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/************************** Constant Definitions ****************************/
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#define AXIPCIE_DEVICE_ID XPAR_AXIPCIE_0_DEVICE_ID
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/*
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* Command register offsets
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*/
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#define PCIE_CFG_CMD_IO_EN 0x00000001 /* I/O access enable */
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#define PCIE_CFG_CMD_MEM_EN 0x00000002 /* Memory access enable */
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#define PCIE_CFG_CMD_BUSM_EN 0x00000004 /* Bus master enable */
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#define PCIE_CFG_CMD_PARITY 0x00000040 /* parity errors response */
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#define PCIE_CFG_CMD_SERR_EN 0x00000100 /* SERR report enable */
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/*
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* PCIe Configuration registers offsets
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*/
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#define PCIE_CFG_ID_REG 0x0000 /* Vendor ID/Device ID offset */
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#define PCIE_CFG_CMD_STATUS_REG 0x0001 /*
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* Command/Status Register
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* Offset
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*/
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#define PCIE_CFG_PRI_SEC_BUS_REG 0x0006 /*
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* Primary/Sec.Bus Register
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* Offset
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*/
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#define PCIE_CFG_CAH_LAT_HD_REG 0x0003 /*
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* Cache Line/Latency Timer/
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* Header Type/
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* BIST Register Offset
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*/
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#define PCIE_CFG_BAR_0_REG 0x0004 /* PCIe Base Addr 0 */
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#define PCIE_CFG_FUN_NOT_IMP_MASK 0xFFFF
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#define PCIE_CFG_HEADER_TYPE_MASK 0x00EF0000
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#define PCIE_CFG_MUL_FUN_DEV_MASK 0x00800000
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#define PCIE_CFG_MAX_NUM_OF_BUS 256
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#define PCIE_CFG_MAX_NUM_OF_DEV 1
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#define PCIE_CFG_MAX_NUM_OF_FUN 8
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#define PCIE_CFG_PRIM_SEC_BUS 0x00070100
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#define PCIE_CFG_HEADER_O_TYPE 0x0000
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#define PCIE_CFG_BAR_0_ADDR 0x00001111
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/**************************** Type Definitions ******************************/
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/***************** Macros (Inline Functions) Definitions ********************/
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/************************** Function Prototypes *****************************/
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int PcieInitRootComplex(XAxiPcie *AxiPciePtr, u16 DeviceId);
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void PCIeEnumerateFabric(XAxiPcie *AxiPciePtr);
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/************************** Variable Definitions ****************************/
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/* Allocate PCIe Root Complex IP Instance */
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XAxiPcie AxiPcieInstance;
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/****************************************************************************/
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/**
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* This function is the entry point for PCIe Root Complex Enumeration Example
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*
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* @param None
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*
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* @return - XST_SUCCESS if successful
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* - XST_FAILURE if unsuccessful.
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*
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* @note None.
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*
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*****************************************************************************/
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int main(void)
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{
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int Status;
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/* Initialize Root Complex */
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Status = PcieInitRootComplex(&AxiPcieInstance, AXIPCIE_DEVICE_ID);
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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}
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/* Scan PCIe Fabric */
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PCIeEnumerateFabric(&AxiPcieInstance);
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return XST_SUCCESS;
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}
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/****************************************************************************/
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/**
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* This function initializes a AXI PCIe IP built as a root complex
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*
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* @param AxiPciePtr is a pointer to an instance of XAxiPcie data
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* structure represents a root complex IP.
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* @param DeviceId is AXI PCIe IP unique ID
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*
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* @return - XST_SUCCESS if successful.
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* - XST_FAILURE if unsuccessful.
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*
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* @note None.
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*
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*
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******************************************************************************/
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int PcieInitRootComplex(XAxiPcie *AxiPciePtr, u16 DeviceId)
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{
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int Status;
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u32 HeaderData;
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u32 InterruptMask;
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u8 BusNumber;
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u8 DeviceNumber;
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u8 FunNumber;
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u8 PortNumber;
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XAxiPcie_Config *ConfigPtr;
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ConfigPtr = XAxiPcie_LookupConfig(DeviceId);
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Status = XAxiPcie_CfgInitialize(AxiPciePtr, ConfigPtr,
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ConfigPtr->BaseAddress);
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if (Status != XST_SUCCESS) {
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xil_printf("Failed to initialize PCIe Root Complex"
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"IP Instance\r\n");
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return XST_FAILURE;
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}
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if(!AxiPciePtr->Config.IncludeRootComplex) {
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xil_printf("Failed to initialize...AXI PCIE is configured"
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" as endpoint\r\n");
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return XST_FAILURE;
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}
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/* See what interrupts are currently enabled */
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XAxiPcie_GetEnabledInterrupts(AxiPciePtr, &InterruptMask);
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xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
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/* Make sure all interrupts disabled. */
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XAxiPcie_DisableInterrupts(AxiPciePtr, XAXIPCIE_IM_ENABLE_ALL_MASK);
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/* See what interrupts are currently pending */
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XAxiPcie_GetPendingInterrupts(AxiPciePtr, &InterruptMask);
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xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
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/* Just if there is any pending interrupt then clear it.*/
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XAxiPcie_ClearPendingInterrupts(AxiPciePtr,
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XAXIPCIE_ID_CLEAR_ALL_MASK);
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/*
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* Read enabled interrupts and pending interrupts
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* to verify the previous two operations and also
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* to test those two API functions
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*/
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XAxiPcie_GetEnabledInterrupts(AxiPciePtr, &InterruptMask);
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xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
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XAxiPcie_GetPendingInterrupts(AxiPciePtr, &InterruptMask);
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xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
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/* Make sure link is up. */
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Status = XAxiPcie_IsLinkUp(AxiPciePtr);
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if (Status != TRUE ) {
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xil_printf("Link is not up\r\n");
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return XST_FAILURE;
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}
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xil_printf("Link is up\r\n");
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/*
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* Read back requester ID.
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*/
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XAxiPcie_GetRequesterId(AxiPciePtr, &BusNumber,
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&DeviceNumber, &FunNumber, &PortNumber);
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xil_printf("Bus Number is %02X\r\n"
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"Device Number is %02X\r\n"
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"Function Number is %02X\r\n"
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"Port Number is %02X\r\n",
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BusNumber, DeviceNumber, FunNumber, PortNumber);
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/* Set up the PCIe header of this Root Complex */
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XAxiPcie_ReadLocalConfigSpace(AxiPciePtr,
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PCIE_CFG_CMD_STATUS_REG, &HeaderData);
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HeaderData |= (PCIE_CFG_CMD_BUSM_EN | PCIE_CFG_CMD_MEM_EN |
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PCIE_CFG_CMD_IO_EN | PCIE_CFG_CMD_PARITY |
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PCIE_CFG_CMD_SERR_EN);
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XAxiPcie_WriteLocalConfigSpace(AxiPciePtr,
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PCIE_CFG_CMD_STATUS_REG, HeaderData);
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/*
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* Read back local config reg.
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* to verify the write.
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*/
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XAxiPcie_ReadLocalConfigSpace(AxiPciePtr,
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PCIE_CFG_CMD_STATUS_REG, &HeaderData);
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xil_printf("PCIe Local Config Space is %8X at register"
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" CommandStatus\r\n", HeaderData);
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/*
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* Set up Bus number
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*/
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HeaderData = PCIE_CFG_PRIM_SEC_BUS;
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XAxiPcie_WriteLocalConfigSpace(AxiPciePtr,
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PCIE_CFG_PRI_SEC_BUS_REG, HeaderData);
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/*
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* Read back local config reg.
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* to verify the write.
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*/
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XAxiPcie_ReadLocalConfigSpace(AxiPciePtr,
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PCIE_CFG_PRI_SEC_BUS_REG, &HeaderData);
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xil_printf("PCIe Local Config Space is %8X at register "
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"Prim Sec. Bus\r\n", HeaderData);
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/* Now it is ready to function */
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xil_printf("Root Complex IP Instance has been successfully"
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" initialized\r\n");
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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* This function enumerates its PCIe system and figures out the nature of each
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* component there like end points,bridges,...
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*
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* @param AxiPciePtr is a pointer to an instance of XAxiPcie
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* data structure represents a root complex IP.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void PCIeEnumerateFabric(XAxiPcie *AxiPciePtr)
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{
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u32 ConfigData;
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u32 PCIeHeaderType;
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u32 PCIeMultiFun;
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u32 PCIeBusNum;
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u32 PCIeDevNum;
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u32 PCIeFunNum;
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u16 PCIeVendorID;
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u32 RegVal;
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xil_printf("Start Enumeration of PCIe Fabric on This System\r\n");
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/* Scan PCIe Fabric */
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for (PCIeBusNum = 0; PCIeBusNum < PCIE_CFG_MAX_NUM_OF_BUS;
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PCIeBusNum++) {
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for (PCIeDevNum = 0; PCIeDevNum < PCIE_CFG_MAX_NUM_OF_DEV;
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PCIeDevNum++) {
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for (PCIeFunNum = 0;
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PCIeFunNum < PCIE_CFG_MAX_NUM_OF_FUN;
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PCIeFunNum++) {
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/* Vendor ID */
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XAxiPcie_ReadRemoteConfigSpace(
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AxiPciePtr,PCIeBusNum,
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PCIeDevNum, PCIeFunNum,
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PCIE_CFG_ID_REG, &ConfigData);
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PCIeVendorID = (u16) (ConfigData & 0xFFFF);
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if (PCIeVendorID ==
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PCIE_CFG_FUN_NOT_IMP_MASK) {
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if (PCIeFunNum == 0)
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/*
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* We don't need to look
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* any further on this device.
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*/
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break;
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}
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else {
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xil_printf("PCIeBus is %02X\r\n"
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"PCIeDev is %02X\r\n"
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"PCIeFunc is %02X\r\n",
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PCIeBusNum, PCIeDevNum,
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PCIeFunNum);
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xil_printf("Vendor ID is %04X \r\n",
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PCIeVendorID);
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/* Header Type */
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XAxiPcie_ReadRemoteConfigSpace(
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AxiPciePtr, PCIeBusNum,
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PCIeDevNum, PCIeFunNum,
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PCIE_CFG_CAH_LAT_HD_REG,
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&ConfigData);
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PCIeHeaderType = ConfigData &
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PCIE_CFG_HEADER_TYPE_MASK;
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PCIeMultiFun = ConfigData &
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PCIE_CFG_MUL_FUN_DEV_MASK;
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if (PCIeHeaderType ==
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PCIE_CFG_HEADER_O_TYPE) {
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/* This is an End Point */
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xil_printf("This is an "
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"End Point\r\n");
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/*
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* Initialize this end point
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* and return.
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*/
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XAxiPcie_ReadRemoteConfigSpace(
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AxiPciePtr,
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PCIeBusNum, PCIeDevNum,
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PCIeFunNum,
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PCIE_CFG_CMD_STATUS_REG,
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&ConfigData);
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ConfigData |=
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(PCIE_CFG_CMD_BUSM_EN |
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PCIE_CFG_CMD_MEM_EN);
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XAxiPcie_WriteRemoteConfigSpace
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(AxiPciePtr,
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PCIeBusNum, PCIeDevNum,
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PCIeFunNum,
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PCIE_CFG_CMD_STATUS_REG,
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ConfigData);
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/*
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* Write Address to
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* PCIe BAR0
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*/
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ConfigData =
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(PCIE_CFG_BAR_0_ADDR |
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PCIeBusNum |
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PCIeDevNum |
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PCIeFunNum);
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XAxiPcie_WriteRemoteConfigSpace
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(AxiPciePtr,
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PCIeBusNum, PCIeDevNum,
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PCIeFunNum, PCIE_CFG_BAR_0_REG,
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ConfigData);
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xil_printf("End Point has been"
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" enabled\r\n");
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}
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else {
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/* This is a bridge */
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xil_printf("This is a "
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"Bridge\r\n");
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}
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}
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if ((!PCIeFunNum) && (!PCIeMultiFun)) {
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/*
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* If it is function 0 and it is not a
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* multi function device, we don't need
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* to look any further on this devie
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*/
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break;
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}
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} /* Functions in one device */
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} /* Devices on the same bus */
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} /* Buses in the same system */
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xil_printf("End of Enumeration of PCIe Fabric on This system\r\n");
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/* Bridge enable */
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XAxiPcie_GetRootPortStatusCtrl(AxiPciePtr, &RegVal);
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RegVal |= XAXIPCIE_RPSC_BRIDGE_ENABLE_MASK;
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XAxiPcie_SetRootPortStatusCtrl(AxiPciePtr, RegVal);
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return;
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}
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