219 lines
8.4 KiB
Tcl
Executable file
219 lines
8.4 KiB
Tcl
Executable file
###############################################################################
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#
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# Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# Use of the Software is limited solely to applications:
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# (a) running on a Xilinx device, or
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# (b) that interact with a Xilinx device through a bus or interconnect.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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# Except as contained in this notice, the name of the Xilinx shall not be used
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# in advertising or otherwise to promote the sale, use or other dealings in
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# this Software without prior written authorization from Xilinx.
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#
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###############################################################################
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##############################################################################
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#
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# Modification History
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#
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# Ver Who Date Changes
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# ----- ---- -------- -----------------------------------------------
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# 1.00a sdm 11/22/11 Created
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# 2.0 adk 10/12/13 Updated as per the New Tcl API's
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# 2.1 adk 11/08/14 Fixed the CR#811288 when PCS/PMA core is present in the hw
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# XPAR_GIGE_PCS_PMA_CORE_PRESENT and phy address values
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# should export to the xparameters.h file.
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# 2.1 bss 09/08/14 Fixed CR#820349 to export phy address in xparameters.h
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# when GMII to RGMII converter is present in hw.
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# 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
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# 1000BASE-X mode export proper values to the xparameters.h
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# file.
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#
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##############################################################################
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#uses "xillib.tcl"
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proc generate {drv_handle} {
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xdefine_zynq_include_file $drv_handle "xparameters.h" "XEmacPs" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_ENET_CLK_FREQ_HZ" "C_ENET_SLCR_1000Mbps_DIV0" "C_ENET_SLCR_1000Mbps_DIV1" "C_ENET_SLCR_100Mbps_DIV0" "C_ENET_SLCR_100Mbps_DIV1" "C_ENET_SLCR_10Mbps_DIV0" "C_ENET_SLCR_10Mbps_DIV1"
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xdefine_zynq_config_file $drv_handle "xemacps_g.c" "XEmacPs" "DEVICE_ID" "C_S_AXI_BASEADDR"
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xdefine_zynq_canonical_xpars $drv_handle "xparameters.h" "XEmacPs" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_ENET_CLK_FREQ_HZ" "C_ENET_SLCR_1000Mbps_DIV0" "C_ENET_SLCR_1000Mbps_DIV1" "C_ENET_SLCR_100Mbps_DIV0" "C_ENET_SLCR_100Mbps_DIV1" "C_ENET_SLCR_10Mbps_DIV0" "C_ENET_SLCR_10Mbps_DIV1"
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generate_gmii2rgmii_params $drv_handle "xparameters.h"
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generate_sgmii_params $drv_handle "xparameters.h"
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}
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proc generate_gmii2rgmii_params {drv_handle file_name} {
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set file_handle [::hsi::utils::open_include_file $file_name]
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set ips [hsi::get_cells "*"]
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foreach ip $ips {
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set ipname [common::get_property NAME $ip]
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set periph [common::get_property IP_NAME $ip]
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if { [string compare -nocase $periph "ps7_ethernet"] == 0} {
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set phya [is_gmii2rgmii_conv_present $ip]
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if { $phya == 0} {
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close $file_handle
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return 0
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}
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puts $file_handle "/* Definition for the MDIO address for the GMII2RGMII converter PL IP*/"
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if { [string compare -nocase $ipname "ps7_ethernet_0"] == 0} {
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puts $file_handle "\#define XPAR_GMII2RGMIICON_0N_ETH0_ADDR $phya"
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}
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if { [string compare -nocase $ipname "ps7_ethernet_1"] == 0} {
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puts $file_handle "\#define XPAR_GMII2RGMIICON_0N_ETH1_ADDR $phya"
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}
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puts $file_handle "\n/******************************************************************/\n"
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}
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}
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close $file_handle
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}
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proc is_gmii2rgmii_conv_present {slave} {
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set port_value 0
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set phy_addr 0
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set ipconv 0
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set ips [hsi::get_cells "*"]
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set enetipinstance_name [common::get_property NAME $slave]
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foreach ip $ips {
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set convipname [common::get_property NAME $ip]
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set periph [common::get_property IP_NAME $ip]
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if { [string compare -nocase $periph "gmii_to_rgmii"] == 0} {
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set ipconv $ip
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break
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}
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}
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if { $ipconv != 0 } {
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set port_value [hsi::get_pins -of_objects [hsi::get_nets -of_objects [hsi::get_pins -of_objects $ipconv gmii_txd]]]
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if { $port_value != 0 } {
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set tmp [string first "ENET0" $port_value]
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if { $tmp >= 0 } {
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if { [string compare -nocase $enetipinstance_name "ps7_ethernet_0"] == 0} {
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set phyaddr [::hsi::utils::get_param_value $ipconv C_PHYADDR]
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set phy_addr [::hsi::utils::convert_binary_to_decimal $phyaddr]
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if {[llength $phy_addr] == 0} {
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set phy_addr 0
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}
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}
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} else {
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set tmp0 [string first "ENET1" $port_value]
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if { $tmp0 >= 0 } {
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if { [string compare -nocase $enetipinstance_name "ps7_ethernet_1"] == 0} {
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set phyaddr [::hsi::utils::get_param_value $ipconv C_PHYADDR]
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set phy_addr [::hsi::utils::convert_binary_to_decimal $phyaddr]
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if {[llength $phy_addr] == 0} {
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set phy_addr 0
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}
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}
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}
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}
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}
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}
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return $phy_addr
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}
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proc generate_sgmii_params {drv_handle file_name} {
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set file_handle [::hsi::utils::open_include_file $file_name]
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set ips [hsi::get_cells "*"]
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foreach ip $ips {
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set ipname [common::get_property NAME $ip]
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set periph [common::get_property IP_NAME $ip]
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if { [string compare -nocase $periph "gig_ethernet_pcs_pma"] == 0} {
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set PhyStandard [common::get_property CONFIG.Standard $ip]
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}
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if { [string compare -nocase $ipname "ps7_ethernet_0"] == 0} {
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set phya [is_gige_pcs_pma_ip_present $ip]
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if { $phya == 0} {
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close $file_handle
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return 0
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}
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if { $PhyStandard == "1000BASEX" } {
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puts $file_handle "/* Definitions related to PCS PMA PL IP*/"
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puts $file_handle "\#define XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT 1"
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puts $file_handle "\#define XPAR_PCSPMA_1000BASEX_PHYADDR $phya"
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puts $file_handle "\n/******************************************************************/\n"
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} else {
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puts $file_handle "/* Definitions related to PCS PMA PL IP*/"
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puts $file_handle "\#define XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT 1"
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puts $file_handle "\#define XPAR_PCSPMA_SGMII_PHYADDR $phya"
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puts $file_handle "\n/******************************************************************/\n"
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}
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}
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}
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close $file_handle
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}
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proc is_gige_pcs_pma_ip_present {slave} {
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set port_value 0
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set phy_addr 0
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set ipconv 0
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set ips [hsi::get_cells "*"]
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set enetipinstance_name [common::get_property IP_NAME $slave]
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foreach ip $ips {
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set convipname [common::get_property NAME $ip]
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set periph [common::get_property IP_NAME $ip]
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if { [string compare -nocase $periph "gig_ethernet_pcs_pma"] == 0} {
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set sgmii_param [common::get_property CONFIG.c_is_sgmii $ip]
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set PhyStandarrd [common::get_property CONFIG.Standard $ip]
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if {$sgmii_param == true || $PhyStandarrd == "1000BASEX"} {
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set ipconv $ip
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}
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break
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}
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}
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if { $ipconv != 0 } {
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set port_value [hsi::get_pins -of_objects [hsi::get_nets -of_objects [hsi::get_pins -of_objects $ipconv gmii_txd]]]
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if { $port_value != 0 } {
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set tmp [string first "ENET0" $port_value]
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if { $tmp >= 0 } {
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if { [string compare -nocase $enetipinstance_name "ps7_ethernet"] == 0} {
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set phyaddr [::hsi::utils::get_param_value $ipconv C_PHYADDR]
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set phy_addr [::hsi::utils::convert_binary_to_decimal $phyaddr]
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if {[llength $phy_addr] == 0} {
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set phy_addr 0
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}
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}
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} else {
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set tmp0 [string first "ENET1" $port_value]
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if { $tmp0 >= 0 } {
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if { [string compare -nocase $enetipinstance_name "ps7_ethernet"] == 0} {
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set phyaddr [::hsi::utils::get_param_value $ipconv C_PHYADDR]
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set phy_addr [::hsi::utils::convert_binary_to_decimal $phyaddr]
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puts [format "phy_addr %s phyaddr %s" $phy_addr $phyaddr]
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if {[llength $phy_addr] == 0} {
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set phy_addr 0
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}
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}
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}
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}
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}
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}
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return $phy_addr
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}
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