a8d64830d6
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
192 lines
6.9 KiB
C
192 lines
6.9 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xdprxss_hw.h
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* @addtogroup dprxss_v1_0
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* @{
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*
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* This header file contains identifiers and register-level core functions (or
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* macros) that can be used to access the Xilinx DisplayPort Receiver Subsystem.
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*
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* For more information about the operation of this core see the hardware
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* specification and documentation in the higher level driver xdprxss.h file.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ---- --- -------- -----------------------------------------------------
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* 1.00 sha 05/18/15 Initial release.
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* </pre>
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*
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******************************************************************************/
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#ifndef XDPRXSS_HW_H_
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#define XDPRXSS_HW_H_ /**< Prevent circular inclusions
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* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/* 0x09C: OVER_LINK_BW_SET */
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#define XDPRXSS_LINK_BW_SET_162GBPS XDP_RX_OVER_LINK_BW_SET_162GBPS /**< 1.62
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* Gbps
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* link
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* rate.
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*/
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#define XDPRXSS_LINK_BW_SET_270GBPS XDP_RX_OVER_LINK_BW_SET_270GBPS /**< 2.70
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* Gbps
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* link
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* rate.
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*/
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#define XDPRXSS_LINK_BW_SET_540GBPS XDP_RX_OVER_LINK_BW_SET_540GBPS /**< 5.40
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* Gbps
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* link
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* rate.
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*/
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/* 0x0A0: OVER_LANE_COUNT_SET */
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#define XDPRXSS_LANE_COUNT_SET_1 XDP_RX_OVER_LANE_COUNT_SET_1 /**< Lane count
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* of 1. */
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#define XDPRXSS_LANE_COUNT_SET_2 XDP_RX_OVER_LANE_COUNT_SET_2 /**< Lane count
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* of 2. */
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#define XDPRXSS_LANE_COUNT_SET_4 XDP_RX_OVER_LANE_COUNT_SET_4 /**< Lane count
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* of 4. */
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#define XDPRXSS_RX_PHY_CONFIG XDP_RX_PHY_CONFIG /**< PHY reset and
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* config */
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#define XDPRXSS_PHY_POWER_DOWN XDP_RX_PHY_POWER_DOWN /**< PHY power down */
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#define XDPRXSS_MSA_HRES XDP_RX_MSA_HRES /**< Number of active pixels
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* per line (the horizontal
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* resolution). */
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#define XDPRXSS_MSA_VRES XDP_RX_MSA_VHEIGHT /**< Number of active
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* lines (the
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* vertical
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* resolution). */
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/* Link bandwidth and lane count setting as exposed in the RX DPCD */
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#define XDPRXSS_DPCD_LINK_BW_SET XDP_RX_DPCD_LINK_BW_SET
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#define XDPRXSS_DPCD_LANE_COUNT_SET XDP_RX_DPCD_LANE_COUNT_SET
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/* Link training status for lanes 0, lane 1, lane 2 and lane 3 as exposed in
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* the RX DPCD
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*/
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#define XDPRXSS_DPCD_LANE01_STATUS XDP_RX_DPCD_LANE01_STATUS
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#define XDPRXSS_DPCD_LANE23_STATUS XDP_RX_DPCD_LANE23_STATUS
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/* Vertical blank interrupt mask */
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#define XDPRXSS_INTR_VBLANK_MASK XDP_RX_INTERRUPT_MASK_VBLANK_MASK
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#define XDPRXSS_NUM_STREAMS 4 /**< Maximum number of
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* streams supported */
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#define XDPRXSS_MAX_NPORTS XDP_MAX_NPORTS /**< Maximum number of
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* RX ports */
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#define XDPRXSS_GUID_NBYTES XDP_GUID_NBYTES /**< Number of bytes
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* for GUID */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/** @name Register access macro definition
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* @{
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*/
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#define XDpRxSs_In32 Xil_In32 /**< Input Operations */
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#define XDpRxSs_Out32 Xil_Out32 /**< Output Operations */
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/*****************************************************************************/
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/**
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*
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* This macro reads a value from a DisplayPort Receiver Subsystem register.
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* A 32 bit read is performed. If the component is implemented in a smaller
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* width, only the least significant data is read from the register. The most
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* significant data will be read as 0.
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*
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* @param BaseAddress is the base address of the XDpRxSs core instance.
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* @param RegOffset is the register offset of the register (defined at
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* the top of this file).
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*
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* @return The 32-bit value of the register.
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*
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* @note C-style signature:
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* u32 XDpRxSs_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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******************************************************************************/
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#define XDpRxSs_ReadReg(BaseAddress, RegOffset) \
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XDpRxSs_In32((BaseAddress) + ((u32)RegOffset))
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/*****************************************************************************/
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/**
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*
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* This macro writes a value to a DisplayPort Receiver Subsystem register.
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* A 32 bit write is performed. If the component is implemented in a smaller
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* width, only the least significant data is written.
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*
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* @param BaseAddress is the base address of the XDpRxSs core instance.
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* @param RegOffset is the register offset of the register (defined at
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* the top of this file) to be written.
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* @param Data is the 32-bit value to write into the register.
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*
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* @return None.
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*
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* @note C-style signature:
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* void XDpRxSs_WriteReg(u32 BaseAddress, u32 RegOffset,
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* u32 Data)
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*
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******************************************************************************/
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#define XDpRxSs_WriteReg(BaseAddress, RegOffset, Data) \
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XDpRxSs_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
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/*@}*/
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/************************** Function Prototypes ******************************/
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/************************** Variable Declarations ****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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/** @} */
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