f37b5011ea
HLS generated driver along with manually written layer 2. Driver tcl update is pending Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
104 lines
4.7 KiB
C
104 lines
4.7 KiB
C
// ==============================================================
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// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
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// Version: 2015.1
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// Copyright (C) 2015 Xilinx Inc. All rights reserved.
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//
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// ==============================================================
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// CTRL
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// 0x00 : Control signals
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// bit 0 - ap_start (Read/Write/COH)
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// bit 1 - ap_done (Read/COR)
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// bit 2 - ap_idle (Read)
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// bit 3 - ap_ready (Read)
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// bit 7 - auto_restart (Read/Write)
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// others - reserved
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// 0x04 : Global Interrupt Enable Register
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// bit 0 - Global Interrupt Enable (Read/Write)
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// others - reserved
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// 0x08 : IP Interrupt Enable Register (Read/Write)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x0c : IP Interrupt Status Register (Read/TOW)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x10 : Data signal of HwReg_width
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// bit 15~0 - HwReg_width[15:0] (Read/Write)
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// others - reserved
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// 0x14 : reserved
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// 0x18 : Data signal of HwReg_height
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// bit 15~0 - HwReg_height[15:0] (Read/Write)
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// others - reserved
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// 0x1c : reserved
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// 0x20 : Data signal of HwReg_input_video_format
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// bit 7~0 - HwReg_input_video_format[7:0] (Read/Write)
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// others - reserved
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// 0x24 : reserved
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// 0x28 : Data signal of HwReg_output_video_format
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// bit 7~0 - HwReg_output_video_format[7:0] (Read/Write)
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// others - reserved
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// 0x2c : reserved
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// 0x30 : Data signal of HwReg_coefs_0_0
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// bit 15~0 - HwReg_coefs_0_0[15:0] (Read/Write)
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// others - reserved
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// 0x34 : reserved
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// 0x38 : Data signal of HwReg_coefs_0_1
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// bit 15~0 - HwReg_coefs_0_1[15:0] (Read/Write)
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// others - reserved
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// 0x3c : reserved
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// 0x40 : Data signal of HwReg_coefs_0_2
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// bit 15~0 - HwReg_coefs_0_2[15:0] (Read/Write)
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// others - reserved
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// 0x44 : reserved
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// 0x48 : Data signal of HwReg_coefs_0_3
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// bit 15~0 - HwReg_coefs_0_3[15:0] (Read/Write)
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// others - reserved
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// 0x4c : reserved
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// 0x50 : Data signal of HwReg_coefs_1_0
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// bit 15~0 - HwReg_coefs_1_0[15:0] (Read/Write)
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// others - reserved
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// 0x54 : reserved
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// 0x58 : Data signal of HwReg_coefs_1_1
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// bit 15~0 - HwReg_coefs_1_1[15:0] (Read/Write)
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// others - reserved
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// 0x5c : reserved
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// 0x60 : Data signal of HwReg_coefs_1_2
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// bit 15~0 - HwReg_coefs_1_2[15:0] (Read/Write)
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// others - reserved
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// 0x64 : reserved
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// 0x68 : Data signal of HwReg_coefs_1_3
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// bit 15~0 - HwReg_coefs_1_3[15:0] (Read/Write)
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// others - reserved
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// 0x6c : reserved
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// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
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#define XV_HCRESAMPLER_CTRL_ADDR_AP_CTRL 0x00
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#define XV_HCRESAMPLER_CTRL_ADDR_GIE 0x04
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#define XV_HCRESAMPLER_CTRL_ADDR_IER 0x08
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#define XV_HCRESAMPLER_CTRL_ADDR_ISR 0x0c
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_WIDTH_DATA 0x10
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_WIDTH_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_HEIGHT_DATA 0x18
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_HEIGHT_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_INPUT_VIDEO_FORMAT_DATA 0x20
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_INPUT_VIDEO_FORMAT_DATA 8
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_OUTPUT_VIDEO_FORMAT_DATA 0x28
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_OUTPUT_VIDEO_FORMAT_DATA 8
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_0_0_DATA 0x30
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_0_0_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_0_1_DATA 0x38
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_0_1_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_0_2_DATA 0x40
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_0_2_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_0_3_DATA 0x48
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_0_3_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_1_0_DATA 0x50
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_1_0_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_1_1_DATA 0x58
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_1_1_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_1_2_DATA 0x60
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_1_2_DATA 16
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#define XV_HCRESAMPLER_CTRL_ADDR_HWREG_COEFS_1_3_DATA 0x68
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#define XV_HCRESAMPLER_CTRL_BITS_HWREG_COEFS_1_3_DATA 16
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