b020c90a28
This patch includes platform specific functions to platform.c and platform.h which are being called by openamp library. The patch also removes Disable DCache API from the application which was being used as a workaround for a cache issue. Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
111 lines
4.4 KiB
C
111 lines
4.4 KiB
C
/*
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* Copyright (c) 2014, Mentor Graphics Corporation
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* All rights reserved.
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Mentor Graphics Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef PLATFORM_H_
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#define PLATFORM_H_
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#include <stdio.h>
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#include "hil.h"
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#include "xil_cache.h"
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#include "xreg_cortexr5.h"
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/* ------------------------- Macros --------------------------*/
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/********************/
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/* Register offsets */
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/********************/
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/* -- FIX ME: ipi info is to be defined -- */
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struct ipi_info {
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uint32_t ipi_base_addr;
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uint32_t ipi_chn_mask;
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};
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int _enable_interrupt(struct proc_vring *vring_hw);
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void _reg_ipi_after_deinit(struct proc_vring *vring_hw);
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void _notify(int cpu_id, struct proc_intr *intr_info);
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int _boot_cpu(int cpu_id, unsigned int load_addr);
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void _shutdown_cpu(int cpu_id);
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void platform_isr(int vect_id, void *data);
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void deinit_isr(int vect_id, void *data);
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#define platform_dcache_all_flush() { Xil_DCacheFlush(); }
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#define platform_dcache_flush_range(addr, len) { Xil_DCacheFlushRange(addr, len); }
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/* IPI REGs OFFSET */
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#define IPI_TRIG_OFFSET 0x00000000 /* IPI trigger register offset */
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#define IPI_OBS_OFFSET 0x00000004 /* IPI observation register offset */
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#define IPI_ISR_OFFSET 0x00000010 /* IPI interrupt status register offset */
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#define IPI_IMR_OFFSET 0x00000014 /* IPI interrupt mask register offset */
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#define IPI_IER_OFFSET 0x00000018 /* IPI interrupt enable register offset */
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#define IPI_IDR_OFFSET 0x0000001C /* IPI interrupt disable register offset */
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/* IPC Device parameters */
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#define SHM_ADDR (void *)0x3ED08000
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#define SHM_SIZE 0x00200000
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#define IPI_BASEADDR 0xff310000
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#define IPI_CHN_BITMASK 0x00000001 /* IPI channel bit mask APU<->RPU0 */
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#define VRING0_IPI_INTR_VECT -1
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#define VRING1_IPI_INTR_VECT 79
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#define MASTER_CPU_ID 0
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#define REMOTE_CPU_ID 1
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#define CORTEXR5_CPSR_INTERRUPTS_BITS (XREG_CPSR_IRQ_ENABLE | XREG_CPSR_FIQ_ENABLE)
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/* This macro writes the current program status register (CPSR - all fields) */
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#define ARM_AR_CPSR_CXSF_WRITE(cpsr_cxsf_value) \
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{ \
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asm volatile(" MSR CPSR_cxsf, %0" \
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: /* No outputs */ \
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: "r" (cpsr_cxsf_value) ); \
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}
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/* This macro sets the interrupt related bits in the status register / control
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register to the specified value. */
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#define ARM_AR_INT_BITS_SET(set_bits) \
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{ \
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int tmp_val; \
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tmp_val = mfcpsr(); \
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tmp_val &= ~((unsigned int)CORTEXR5_CPSR_INTERRUPTS_BITS); \
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tmp_val |= set_bits; \
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ARM_AR_CPSR_CXSF_WRITE(tmp_val); \
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}
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/* This macro gets the interrupt related bits from the status register / control
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register. */
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#define ARM_AR_INT_BITS_GET(get_bits_ptr) \
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{ \
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int tmp_val; \
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tmp_val = mfcpsr(); \
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tmp_val &= CORTEXR5_CPSR_INTERRUPTS_BITS; \
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*get_bits_ptr = tmp_val; \
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}
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#endif /* PLATFORM_H_ */
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