2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
673 lines
25 KiB
C
Executable file
673 lines
25 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xsrio_hw.h
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*
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* This header file contains identifiers and macros that can be used to access
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* the Axi srio gen2 device. The driver APIs/functions are defined in
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* xsrio.h.
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*
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* @note
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*
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------------
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* 1.0 adk 16/04/14 Initial release.
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*
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******************************************************************************/
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#ifndef XSRIO_HW_H /* prevent circular inclusions */
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#define XSRIO_HW_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "xil_types.h"
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#include "xil_io.h"
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/*
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* Register offset definitions. Unless otherwise noted, register access is
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* 32 bit.
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*/
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/** @name Device registers
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* @{
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*/
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/**
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* Capability Address Register Space 0x00-0x3C Registers
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*/
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#define XSRIO_DEV_ID_CAR_OFFSET 0x00 /**< Device Identity CAR */
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#define XSRIO_DEV_INFO_CAR_OFFSET 0x04 /**< Device Information CAR */
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#define XSRIO_ASM_ID_CAR_OFFSET 0x08 /**< Assembly Identity CAR */
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#define XSRIO_ASM_INFO_CAR_OFFSET 0x0C /**< Assembly Information CAR */
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#define XSRIO_PEF_CAR_OFFSET 0x10 /**< Processing Element
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* Features CAR
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*/
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#define XSRIO_SWP_INFO_CAR_OFFSET 0x14 /**< Switch Port Information CAR */
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#define XSRIO_SRC_OPS_CAR_OFFSET 0x18 /**< Source operations CAR */
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#define XSRIO_DST_OPS_CAR_OFFSET 0x1c /**< Destination operations CAR */
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/**
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* Command and Status Register Space 0x040-0xFC Registers
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*/
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#define XSRIO_PELL_CTRL_CSR_OFFSET 0x4c /**< PE Logical layer
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* Control CSR
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*/
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#define XSRIO_LCS0_BASEADDR_CSR_OFFSET 0x58 /**< Local Configuration
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* Space 0 Base Address CSR
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*/
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#define XSRIO_LCS1_BASEADDR_CSR_OFFSET 0x5c /**< Local Configuration
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* Space 1 Base Address CSR
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*/
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#define XSRIO_BASE_DID_CSR_OFFSET 0x60 /**< Base Device ID CSR */
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#define XSRIO_HOST_DID_LOCK_CSR_OFFSET 0x68 /**< Host Base Device ID
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* Lock CSR
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*/
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#define XSRIO_COMPONENT_TAG_CSR_OFFSET 0x6c /**< Component Tag CSR */
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/**
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* Extended Feature Register Space 0x0100-0xFFFC Registers
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*/
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#define XSRIO_EFB_HEADER_OFFSET 0x100 /**< Extended features LP
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* Serial Register Block Header
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*/
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#define XSRIO_PORT_LINK_TOUT_CSR_OFFSET 0x120 /**< Port Link Timeout CSR */
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#define XSRIO_PORT_RESP_TOUT_CSR_OFFSET 0x124 /**< Port Response Timeout
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* CSR
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*/
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#define XSRIO_PORT_GEN_CTL_CSR_OFFSET 0x13c /**< General Control CSR */
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#define XSRIO_PORT_N_MNT_REQ_CSR_OFFSET 0x140 /**< Port n Link Maintenance
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* Request CSR
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*/
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#define XSRIO_PORT_N_MNT_RES_CSR_OFFSET 0x144 /**< Port n Maintenance
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* Response CSR
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*/
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#define XSRIO_PORT_N_ACKID_CSR_OFFSET 0x148 /**< Port n Local Ack ID CSR */
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#define XSRIO_PORT_N_ERR_STS_CSR_OFFSET 0x158 /**< Port n Error and
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* Status CSR
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*/
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#define XSRIO_PORT_N_CTL_CSR_OFFSET 0x15c /**< Port n Control CSR */
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#define XSRIO_EFB_LPSL_OFFSET 0x0400 /**< LP-Serial Lane Extended
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* Features offset
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*/
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#define XSRIO_SL_HEADER_OFFSET 0x00 /**< Serial Lane Block Header */
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#define XSRIO_SLS0_CSR_OFFSET(n) (0x10 + n*0x20)
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/**< Serial Lane N
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* Status 0 CSR
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*/
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#define XSRIO_SLS1_CSR_OFFSET(n) (0x14 + n*0x20)
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/**< Serial Lane N
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* Status 1 CSR
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*/
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/**
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* Implementation Defined Space 0x010000 - 0xFFFFFC Registers
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*/
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#define XSRIO_IMP_WCSR_OFFSET 0x10000 /**< Water Mark CSR */
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#define XSRIO_IMP_BCSR_OFFSET 0x10004 /**< Buffer Control CSR */
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#define XSRIO_IMP_MRIR_OFFSET 0x10100 /**< Maintenance Request
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* Information Register
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*/
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/*@}*/
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/** @name Device Identity CAR bit definitions.
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* These bits are associated with the XSRIO_DEV_ID_CAR_OFFSET register.
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* @{
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*/
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#define XSRIO_DEV_ID_DEVID_CAR_MASK 0xFFFF0000 /**< Device ID Mask */
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#define XSRIO_DEV_ID_VDRID_CAR_MASK 0x0000FFFF /**< Device Vendor ID Mask */
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#define XSRIO_DEV_ID_DEVID_CAR_SHIFT 16 /**< Device ID shift */
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/*@}*/
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/** @name Device Information CAR bit definitions.
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* These bits are associated with the XSRIO_DEV_INFO_CAR_OFFSET register.
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* @{
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*/
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#define XSRIO_DEV_INFO_CAR_PATCH_MASK 0x0000000F /**< Patch Mask */
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#define XSRIO_DEV_INFO_CAR_MINREV_MASK 0x000000F0 /**< Minor Revision Mask */
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#define XSRIO_DEV_INFO_CAR_MAJREV_MASK 0x00000F00 /**< Major Revision Mask */
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#define XSRIO_DEV_INFO_CAR_DEVREV_MASK 0x000F0000 /**< Device Revision
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* Lable Mask
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*/
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/*@}*/
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/** @name Assembly Identity CAR bit definitions.
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* These bits are associated with the XSRIO_ASM_ID_CAR_OFFSET register.
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* @{
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*/
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#define XSRIO_ASM_ID_CAR_ASMID_MASK 0xFFFF0000 /**< Assembly ID Mask */
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#define XSRIO_ASM_ID_CAR_ASMVID_MASK 0x0000FFFF /**< Assembly Vendor ID Mask */
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#define XSRIO_ASM_ID_CAR_ASMID_SHIFT 16 /**< Assembly ID Shift */
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/*@}*/
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/** @name Assembly Device Information CAR bit definitions.
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* These bits are associated with the XSRIO_ASM_INFO_CAR_OFFSET register.
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* @{
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*/
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#define XSRIO_ASM_INFO_CAR_ASMREV_MASK 0xFFFF0000 /**< Assembly Revision
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* Mask
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*/
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#define XSRIO_ASM_INFO_CAR_EFP_MASK 0x0000FFFF /**< Extended Features
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* Pointer Mask
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*/
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#define XSRIO_ASM_INFO_CAR_ASMREV_SHIFT 16 /**< Assembly Revision Shift */
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/*@}*/
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/** @name Processing Element Features CAR bit definitions.
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* These bits are associated with the XSRIO_PEF_CAR_OFFSET register.
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* @{
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*/
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#define XSRIO_PEF_CAR_EAS_MASK 0x00000007 /**< Extended Addressing
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* Support Mask
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*/
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#define XSRIO_PEF_CAR_EF_MASK 0x00000008 /**< Extended Features Mask */
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#define XSRIO_PEF_CAR_CTS_MASK 0x00000010 /**< Common Transport Large
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* System support Mask
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*/
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#define XSRIO_PEF_CAR_CRF_MASK 0x00000020 /**< CRF Support Mask */
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#define XSRIO_PEF_CAR_MPORT_MASK 0x08000000 /**< Multi Port Mask */
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#define XSRIO_PEF_CAR_SWITCH_MASK 0x10000000 /**< Switch Mask */
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#define XSRIO_PEF_CAR_PROCESSOR_MASK 0x20000000 /**< Processor Mask */
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#define XSRIO_PEF_CAR_MEMORY_MASK 0x40000000 /**< Memory Mask */
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#define XSRIO_PEF_CAR_BRIDGE_MASK 0x80000000 /**< Bridge Mask */
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/*@}*/
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/** @name Source Operations CAR bit definitions.
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* These bits are associated with the XSRIO_SRC_OPS_CAR_OFFSET
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* register and XSRIO_DST_OPS_CAR register.
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* @{
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*/
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#define XSRIO_SRCDST_OPS_CAR_PORT_WRITE_MASK 0x00000004 /**< Port write
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* operation Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_ATOMIC_SWP_MASK 0x00000008 /**< Atomic Swap
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* Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_ATOMIC_CLR_MASK 0x00000010 /**< Atomic Clear
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* Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_ATOMIC_SET_MASK 0x00000020 /**< Atomic Set
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* Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_ATOMIC_DECR_MASK 0x00000040 /**< Atomic
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* Decrement Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_ATOMIC_INCR_MASK 0x00000080 /**< Atomic
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* Increment Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_ATOMIC_TSWP_MASK 0x00000100 /**< Atomic test
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* and swap Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_ATOMIC_CSWP_MASK 0x00000200 /**< Atomic compare
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* and Swap Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_DOORBELL_MASK 0x00000400 /**< Doorbell Mask */
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#define XSRIO_SRCDST_OPS_CAR_DATA_MSG_MASK 0x00000800 /**< Data Message
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* Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_WRITE_RESPONSE_MASK 0x00001000 /**< Write with
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* Response Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_SWRITE_MASK 0x00002000 /**< Streaming
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* Write Mask
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*/
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#define XSRIO_SRCDST_OPS_CAR_WRITE_MASK 0x00004000 /**< Write Mask */
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#define XSRIO_SRCDST_OPS_CAR_READ_MASK 0x00008000 /**< Read Mask */
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/*@}*/
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/** @name PE Logical layer Control CSR bit definitions.
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* These bits are associated with the XSRIO_PELL_CTRL_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PELL_CTRL_CSR_EAC_MASK 0x00000007 /**< Extended Addressing
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* Control Mask
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*/
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/*@}*/
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/** @name Local Configuration Space Base Address 1 CSR bit definitions.
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* These bits are associated with the XSRIO_LCS1_BASEADDR_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_LCS1_BASEADDR_LCSBA_CSR_MASK 0x7FE00000 /**< LCSBA Mask */
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#define XSRIO_LCS1_BASEADDR_LCSBA_CSR_SHIFT 21 /**< LCSBA Shift */
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/*@}*/
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/** @name Base Device ID CSR bit definitions.
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* These bits are associated with the XSRIO_BASE_DID_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_BASE_DID_CSR_LBDID_MASK 0x0000FFFF /**< Large Base Device ID
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* Mask(16-bit device ID)
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*/
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#define XSRIO_BASE_DID_CSR_BDID_MASK 0x00FF0000 /**< Base Device ID
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* Mask(8-bit device ID)
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*/
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#define XSRIO_BASE_DID_CSR_BDID_SHIFT 16 /**< Base Device ID Shift */
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/*@}*/
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/** @name Host Base Device ID CSR bit definitions.
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* These bits are associated with the XSRIO_HOST_DID_LOCK_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_HOST_DID_LOCK_CSR_HBDID_MASK 0x0000FFFF /**< Host Base
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* Device ID Mask
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*/
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/*@}*/
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/** @name LP - Serial Register Block header bit definitions.
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* These bits are associated with the XSRIO_EFB_HEADER_OFFSET register.
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* @{
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*/
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#define XSRIO_EFB_HEADER_EFID_MASK 0x0000FFFF /**< Extended Features ID
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* Mask
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*/
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#define XSRIO_EFB_HEADER_EFP_MASK 0xFFFF0000 /**< Extended Features
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* Pointer Mask
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*/
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#define XSRIO_EFB_HEADER_EFP_SHIFT 16 /**< Extended Features
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* Pointer Shift
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*/
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/*@}*/
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/** @name Port Link timeout value CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_LINK_TOUT_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_MASK 0xFFFFFF00 /**< Timeout Value
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* Mask
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*/
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#define XSRIO_PORT_LINK_TOUT_CSR_TOUTVAL_SHIFT 8 /**< Timeout Value
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* Shift
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*/
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/*@}*/
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/** @name Port response timeout value CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_RESP_TOUT_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_MASK 0xFFFFFF00 /**< Response Timeout
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* Value Mask
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*/
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#define XSRIO_PORT_RESP_TOUT_CSR_TOUTVAL_SHIFT 8 /**< Response Timeout
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* Shift
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*/
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/*@}*/
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/** @name Port General Control CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_GEN_CTL_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_GEN_CTL_CSR_DISCOVERED_MASK 0x20000000 /**< Discovered Mask */
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#define XSRIO_PORT_GEN_CTL_CSR_MENABLE_MASK 0x40000000 /**< Master Enable Mask */
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#define XSRIO_PORT_GEN_CTL_CSR_HOST_MASK 0x80000000 /**< Host Mask */
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/*@}*/
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/** @name Port n maintenance request CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_N_MNT_REQ_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_N_MNT_REQ_CSR_CMD_MASK 0x00000007 /**< Command Mask */
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/*@}*/
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/** @name Port n maintenance response CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_N_MNT_RES_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_N_MNT_RES_CSR_LS_MASK 0x0000001F /**< link status Mask */
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#define XSRIO_PORT_N_MNT_RES_CSR_ACKS_MASK 0x000007E0 /**< Ack ID status
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* Mask
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*/
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#define XSRIO_PORT_N_MNT_RES_CSR_RVALID_MASK 0x80000000 /**< Response Valid
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* Mask
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*/
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/*@}*/
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/** @name Port n local ack ID CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_N_ACKID_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_N_ACKID_CSR_OBACKID_MASK 0x0000003F /**< Out bound
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* ACK ID Mask
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*/
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#define XSRIO_PORT_N_ACKID_CSR_OSACKID_MASK 0x00003F00 /**< Out Standing
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* ACK ID Mask
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*/
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#define XSRIO_PORT_N_ACKID_CSR_IBACKID_MASK 0x3F000000 /**< In bound
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* ACK ID Mask
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*/
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#define XSRIO_PORT_N_ACKID_CSR_CLSACKID_MASK 0x80000000 /**< Clear
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* Outstanding
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* ACK ID Mask
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*/
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#define XSRIO_PORT_N_ACKID_CSR_RESET_OBACKID_MASK 0xFFFFFFC0 /**< Out bound ACK
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* ID Reset Mask
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*/
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#define XSRIO_PORT_N_ACKID_CSR_RESET_IBACKID_MASK 0xC0FFFFFF /**< In bound ACK
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* ID Reset Mask
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*/
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#define XSRIO_PORT_N_ACKID_CSR_IBACKID_SHIFT 24 /**< In bound
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* ACK ID shift
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*/
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/*@}*/
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/** @name Port n Error and Status CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_N_ERR_STS_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_PUINT_MASK 0x00000001 /**< Port
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* un-initialized Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_POK_MASK 0x00000002 /**< Port Ok Mask */
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#define XSRIO_PORT_N_ERR_STS_CSR_PERR_MASK 0x00000004 /**< Port Error Mask */
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#define XSRIO_PORT_N_ERR_STS_CSR_IERRS_MASK 0x00000100 /**< Input Error
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* stopped Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_IERRE_MASK 0x00000200 /**< Input Error
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* encountered Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_IRTS_MASK 0x00000400 /**< Input Retry
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* Stopped Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_OERRS_MASK 0x00010000 /**< Output error
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* Stopped Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_OERRE_MASK 0x00020000 /**< Output error
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* encountered Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_ORTS_MASK 0x00040000 /**< Output Retry
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* Stopped Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_OR_MASK 0x00080000 /**< Output
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* Retried Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_ORE_MASK 0x00100000 /**< Output Retry
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* Encountered Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_FLOWCNTL_MASK 0x08000000 /**< Flow Control
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* Mode Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQ_MASK 0x20000000 /**< Idle sequence
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* Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQE_MASK 0x40000000 /**< Idle sequence 2
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* Enable Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_IDL_SEQS_MASK 0x80000000 /**< Idle sequence 2
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* support Mask
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*/
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#define XSRIO_PORT_N_ERR_STS_CSR_ERR_ALL_MASK 0x001FFF07 /**< Port Errors Mask */
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/*@}*/
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/** @name Port n Control CSR bit definitions.
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* These bits are associated with the XSRIO_PORT_N_CTL_CSR_OFFSET register.
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* @{
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*/
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#define XSRIO_PORT_N_CTL_CSR_PTYPE_MASK 0x00000001 /**< Port Type Mask */
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#define XSRIO_PORT_N_CTL_CSR_EPWDS_MASK 0x00003000 /**< Extended Port
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* Width Support Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_EPWOR_MASK 0x0000C000 /**< Extended Port
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* Width Override Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_ENUMB_MASK 0x00020000 /**< Enumeration
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* Boundary Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_MCENT_MASK 0x00080000 /**< Multi-cast Event
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* Participant Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_ERRD_MASK 0x00100000 /**< Error Checking
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* Disable Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_IPE_MASK 0x00200000 /**< Input port
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* enable Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_OPE_MASK 0x00400000 /**< Output port
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* enable Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_PD_MASK 0x00800000 /**< Output port
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* disable Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_PWO_MASK 0x07000000 /**< Port width
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* Override Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_RESET_PWO_MASK 0xF8FFFFFF /**< Port width
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* Override Reset Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_IPW_MASK 0x38000000 /**< Initialized
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* Port width Mask
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*/
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#define XSRIO_PORT_N_CTL_CSR_PW_MASK 0xc0000000 /**< Port width Mask */
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#define XSRIO_PORT_N_CTL_CSR_STATUS_ALL_MASK 0x00F00000 /**< Port Status All
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* Mask
|
|
*/
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|
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#define XSRIO_PORT_N_CTL_CSR_PWO_SHIFT 24 /**< Port width
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* Override Shift
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|
*/
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#define XSRIO_PORT_N_CTL_CSR_PW_SHIFT 30 /**< Port width
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* Shift
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|
*/
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/*@}*/
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/** @name LP -Serial Lane Register Block Header bit definitions.
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* These bits are associated with the XSRIO_SL_HEADER_OFFSET register.
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* @{
|
|
*/
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#define XSRIO_SL_HEADER_EFID_MASK 0x0000FFFF /**< Extended
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* Features ID Mask
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|
*/
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#define XSRIO_SL_HEADER_EFP_MASK 0xFFFF0000 /**< Extended Features
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* Pointer Mask
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*/
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#define XSRIO_SL_HEADER_EFP_SHIFT 16 /**< Extended Features
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* Pointer Shift
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|
*/
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/*@}*/
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|
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/** @name LP -Seral Lane n Status 0 CSRS bit definitions.
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* These bits are associated with the XSRIO_SLS0_CSR(x) register.
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* @{
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|
*/
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#define XSRIO_SLS0_CSR_PORT_NUM_MASK 0xFF000000 /**< Port Number Mask */
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#define XSRIO_SLS0_CSR_LANE_NUM_MASK 0x00F00000 /**< Lane Number Mask */
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#define XSRIO_SLS0_CSR_TRANSMIT_TYPE_MASK 0x00080000 /**< Transmitter
|
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* Type Mask
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|
*/
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#define XSRIO_SLS0_CSR_TRANSMIT_MODE_MASK 0x00040000 /**< Transmitter
|
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* Mode Mask
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|
*/
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#define XSRIO_SLS0_CSR_RCV_INPUT_INV_MASK 0x00008000 /**< Receiver Input
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* Inverted Mask
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|
*/
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#define XSRIO_SLS0_CSR_RCV_TRAINED_MASK 0x00004000 /**< Receiver
|
|
* Trained Mask
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|
*/
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#define XSRIO_SLS0_CSR_RCVLANE_SYNC_MASK 0x00002000 /**< Receive Lane
|
|
* Sync Mask
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|
*/
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|
#define XSRIO_SLS0_CSR_RCVLANE_RDY_MASK 0x00001000 /**< Receive Lane
|
|
* Ready Mask
|
|
*/
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|
#define XSRIO_SLS0_CSR_DECODING_ERRORS_MASK 0x00000F00 /**< 8B/10B Decoding
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|
* errors Mask
|
|
*/
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|
#define XSRIO_SLS0_CSR_LANESYNC_CHAN_MASK 0x00000080 /**< lane_sync state
|
|
* change Mask
|
|
*/
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|
#define XSRIO_SLS0_CSR_RCVTRAINED_CHAN_MASK 0x00000040 /**< rcvr_train state
|
|
* changed Mask
|
|
*/
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#define XSRIO_SLS0_CSR_STAT1_IMP_MASK 0x00000008 /**< Status 1 CSR
|
|
* Implemented Mask
|
|
*/
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|
#define XSRIO_SLS0_CSR_DECODING_ERRORS_SHIFT 8
|
|
/*@}*/
|
|
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/** @name LP -Seral Lane n Status 1 CSRS bit definitions.
|
|
* These bits are associated with the XSRIO_SLS1_CSR(x) register.
|
|
* @{
|
|
*/
|
|
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|
#define XSRIO_SLS1_CSR_SCRDSCR_EN_MASK 0x00008000 /**< Connected port
|
|
* Scrambling/Descrambling
|
|
* Enabled Mask
|
|
*/
|
|
#define XSRIO_SLS1_CSR_CPTEIS_MASK 0x00030000 /**< Connected port transmit
|
|
* Emphasis Tap(+1) Status
|
|
* Mask
|
|
*/
|
|
#define XSRIO_SLS1_CSR_CPTEDS_MASK 0x000C0000 /**< Connected port transmit
|
|
* Emphasis Tap(-1) Status
|
|
* Mask
|
|
*/
|
|
#define XSRIO_SLS1_CSR_LANENUM_MASK 0x00F00000 /**< Lane number within
|
|
* connected port
|
|
*/
|
|
#define XSRIO_SLS1_CSR_RXPORT_WIDTH_MASK 0x07000000 /**< Receive port width
|
|
* Mask
|
|
*/
|
|
#define XSRIO_SLS1_CSR_CPLR_TRAINED_MASK 0x08000000 /**< Connected port lane
|
|
* Receiver trained Mask
|
|
*/
|
|
#define XSRIO_SLS1_CSR_IMPDEFINED_MASK 0x10000000 /**< Implementation defined
|
|
* Mask
|
|
*/
|
|
#define XSRIO_SLS1_CSR_VALCHANGED_MASK 0x20000000 /**< Values Changed Mask */
|
|
#define XSRIO_SLS1_CSR_IDLE2_INFO_MASK 0x40000000 /**< IDLE2 Information
|
|
* Current Mask
|
|
*/
|
|
#define XSRIO_SLS1_CSR_IDLE2_REC_MASK 0x80000000 /**< IDLE2 Received Mask */
|
|
/*@}*/
|
|
|
|
/** @name Water Mark CSRS bit definitions.
|
|
* These bits are associated with the XSRIO_IMP_WCSR_OFFSET register.
|
|
* @{
|
|
*/
|
|
|
|
#define XSRIO_IMP_WCSR_WM2_MASK 0x003F0000 /**< Water Mark 2 Mask */
|
|
#define XSRIO_IMP_WCSR_WM1_MASK 0x00003F00 /**< Water Mark 1 Mask */
|
|
#define XSRIO_IMP_WCSR_WM0_MASK 0x0000003F /**< Water Mark 0 Mask */
|
|
#define XSRIO_IMP_WCSR_WM1_SHIFT 8 /**< Water Mark 1 Shift */
|
|
#define XSRIO_IMP_WCSR_WM2_SHIFT 16 /**< Water Mark 2 Shift */
|
|
/*@}*/
|
|
|
|
/** @name Buffer Control CSRS bit definitions.
|
|
* These bits are associated with the XSRIO_IMP_BCSR_OFFSET register.
|
|
* @{
|
|
*/
|
|
#define XSRIO_IMP_BCSR_RXFLOW_CNTLONLY_MASK 0x80000000 /**< Rx Flow Control
|
|
* Only Mask
|
|
*/
|
|
#define XSRIO_IMP_BCSR_UNIFIED_CLK_MASK 0x40000000 /**< Buffer Control
|
|
* Mask
|
|
*/
|
|
#define XSRIO_IMP_BCSR_TX_FLOW_CNTL_MASK 0x20000000 /**< Tx Flow
|
|
* Control Mask
|
|
*/
|
|
#define XSRIO_IMP_BCSR_TXREQ_REORDER_MASK 0x10000000 /**< Tx Request
|
|
* Reorder Mask */
|
|
#define XSRIO_IMP_BCSR_TXSIZE_MASK 0x07FF0000 /**< Tx size Mask */
|
|
#define XSRIO_IMP_BCSR_FRX_FLOW_CNTL_MASK 0x00008000 /**< Force Rx flow
|
|
* Control Mask
|
|
*/
|
|
#define XSRIO_IMP_BCSR_RXSIZE_MASK 0x000000FF /**< Rx size Mask */
|
|
#define XSRIO_IMP_BCSR_TXSIZE_SHIFT 16 /**< Tx size shift */
|
|
/*@}*/
|
|
|
|
/** @name Maintenance Request Information Register bit definitions.
|
|
* These bits are associated with the XSRIO_IMP_MRIR_OFFSET register.
|
|
* @{
|
|
*/
|
|
#define XSRIO_IMP_MRIR_REQ_TID_MASK 0xFF000000 /**< Request TID Mask */
|
|
#define XSRIO_IMP_MRIR_REQ_PRIO_MASK 0x00060000 /**< Request Priority Mask */
|
|
#define XSRIO_IMP_MRIR_REQ_CRF_MASK 0x00010000 /**< Request CRF Mask */
|
|
#define XSRIO_IMP_MRIR_REQ_DESTID_MASK 0x0000FFFF /**< Request Destination
|
|
* ID Mask
|
|
*/
|
|
#define XSRIO_IMP_MRIR_REQ_PRIO_SHIFT 17
|
|
#define XSRIO_IMP_MRIR_REQ_CRF_SHIFT 16
|
|
#define XSRIO_IMP_MRIR_REQ_TID_SHIFT 24
|
|
|
|
/*@}*/
|
|
|
|
/****************** Macros (Inline Functions) Definitions ********************/
|
|
/*****************************************************************************/
|
|
/**
|
|
* Macro to read register.
|
|
*
|
|
* @param BaseAddress is the base address of the SRIO
|
|
* @param RegOffset is the register offset.
|
|
*
|
|
* @return Value of the register.
|
|
*
|
|
* @note C-style signature:
|
|
* u32 XSrio_ReadReg(u32 BaseAddress, u32 RegOffset)
|
|
*
|
|
******************************************************************************/
|
|
#define XSrio_ReadReg(BaseAddress, RegOffset) \
|
|
Xil_In32((BaseAddress) + (RegOffset))
|
|
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
* Macro to write register.
|
|
*
|
|
* @param BaseAddress is the base address of the SRIO.
|
|
* @param RegOffset is the register offset.
|
|
* @param Data is the data to write.
|
|
*
|
|
* @return None
|
|
*
|
|
* @note C-style signature:
|
|
* void XSRIO_WriteReg(u32 BaseAddress, u32 RegOffset,
|
|
* u32 Data)
|
|
*
|
|
******************************************************************************/
|
|
#define XSrio_WriteReg(BaseAddress, RegOffset, Data) \
|
|
Xil_Out32((BaseAddress) + (RegOffset), (Data))
|
|
/*************************** Variable Definitions ****************************/
|
|
|
|
/*************************** Function Prototypes *****************************/
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* end of protection macro */
|
|
|