24e51cb0b1
Use proper value for XTG_ID_MASK. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
520 lines
18 KiB
C
Executable file
520 lines
18 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xtrafgen_hw.h
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*
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* This header file contains identifiers and macros that can be used to access
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* the Axi Traffic Generator device. The driver APIs/functions are defined in
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* xtrafgen.h.
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*
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* @note
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------------
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* 1.00a srt 1/12/13 First release
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* 1.01a adk 03/09/13 Updated Driver to Support Static and Streaming Mode
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* 2.00a adk 16/09/13 Fixed CR:737291
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* 2.01a adk 21/10/13 Fixed CR:740522 Updated the MasterRam offset as per latest
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* IP.This driver is valid only for IP(v2.0) onwards. The
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* XTG_MASTER_RAM_OFFSET has been changed from
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* 0x10000 to 0xc000.
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* 2.01a adk 15/11/13 Fixed CR:760808 Added Mask for the New bit field added
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* (XTG_MCNTL_LOOPEN_MASK).
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* 3.1 adk 28/04/14 Fixed CR:782131 Incorrect Mask value for the loopenable
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* bit.
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*
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* </pre>
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******************************************************************************/
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#ifndef XTRAFGEN_HW_H /* prevent circular inclusions */
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#define XTRAFGEN_HW_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "xil_types.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/*
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* Register offset definitions. Unless otherwise noted, register access is
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* 32 bit.
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*/
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/** @name Device registers
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* @{
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*/
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#define XTG_MCNTL_OFFSET 0x00 /**< Master Control */
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#define XTG_SCNTL_OFFSET 0x04 /**< Slave Control */
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#define XTG_ERR_STS_OFFSET 0x08 /**< Error Status */
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#define XTG_ERR_EN_OFFSET 0x0C /**< Error Enable */
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#define XTG_MSTERR_INTR_OFFSET 0x10 /**< Master Err Interrupt Enable */
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#define XTG_CFG_STS_OFFSET 0x14 /**< Config Status */
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#define XTG_STREAM_CNTL_OFFSET 0x30 /**< Streaming Control */
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#define XTG_STREAM_CFG_OFFSET 0x34 /**< Streaming Config */
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#define XTG_STREAM_TL_OFFSET 0x38 /**< Streaming Transfer Length */
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/**
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* Static Mode Register Descrptions
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*/
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#define XTG_STATIC_CNTL_OFFSET 0x60 /**< Static Control */
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#define XTG_STATIC_LEN_OFFSET 0x64 /**< Static Length */
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/*@}*/
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/** @name Internal RAM Offsets
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* @{
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*/
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#define XTG_PARAM_RAM_OFFSET 0x1000 /**< Parameter RAM Offset */
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#define XTG_COMMAND_RAM_OFFSET 0x8000 /**< Command RAM Offset */
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#define XTG_MASTER_RAM_OFFSET 0xC000 /**< Master RAM Offset */
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/*@}*/
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/** @name Master Control Register bit definitions.
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* These bits are associated with the XTG_MCNTL_OFFSET register.
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* @{
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*/
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#define XTG_MCNTL_REV_MASK 0xFF000000 /**< Core Revision Mask */
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#define XTG_MCNTL_MSTID_MASK 0x00E00000 /**< M_ID_WIDTH Mask */
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#define XTG_MCNTL_MSTEN_MASK 0x00100000 /**< Master Logic Enable
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Mask */
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#define XTG_MCNTL_LOOPEN_MASK 0x00080000 /**< Loop enable Mask */
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#define XTG_MCNTL_REV_SHIFT 24 /**< Core Rev shift */
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#define XTG_MCNTL_MSTID_SHIFT 21 /**< M_ID_WIDTH shift */
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/*@}*/
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/** @name Slave Control Register bit definitions.
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* These bits are associated with the XTG_SCNTL_OFFSET register.
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* @{
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*/
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#define XTG_SCNTL_BLKRD_MASK 0x00080000 /**< Enable
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Block Read */
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#define XTG_SCNTL_DISEXCL_MASK 0x00040000 /**< Disable
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Exclusive Access */
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#define XTG_SCNTL_WORDR_MASK 0x00020000 /**< Write Response
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Order Enable */
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#define XTG_SCNTL_RORDR_MASK 0x00010000 /**< Read Response
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Order Enable */
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#define XTG_SCNTL_ERREN_MASK 0x00008000 /**< Slv Error
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Interrupt Enable */
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/*@}*/
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/** @name Error bitmasks
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* These bits are shared with the XTG_ERR_STS_OFFSET and
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* XTG_ERR_EN_OFFSET register.
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* @{
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*/
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#define XTG_ERR_ALL_MSTERR_MASK 0x001F0000 /**< Master
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Errors Mask */
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#define XTG_ERR_ALL_SLVERR_MASK 0x00000003 /**< Slave
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Errors Mask */
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#define XTG_ERR_ALL_ERR_MASK 0x001F0003 /**< All
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Errors Mask */
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#define XTG_ERR_MSTCMP_MASK 0x80000000 /**< Master
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Complete Mask */
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#define XTG_ERR_RIDER_MASK 0x00100000 /**< Master
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Invalid
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RVALID Mask */
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#define XTG_ERR_WIDER_MASK 0x00080000 /**< Master
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Invalid
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BVALID Mask */
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#define XTG_ERR_WRSPER_MASK 0x00040000 /**< MW
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Invalid
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RESP Mask */
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#define XTG_ERR_RERRSP_MASK 0x00020000 /**< MR
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Invalid
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RESP Mask */
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#define XTG_ERR_RLENER_MASK 0x00010000 /**< Master
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Read Length
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Mask */
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#define XTG_ERR_SWSTRB_MASK 0x00000002 /**< Slave
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WSTRB Illegal
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Mask */
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#define XTG_ERR_SWLENER_MASK 0x00000001 /**< Slave
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Read Length
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Mask */
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/*@}*/
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/*@}*/
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/** @name Master Error Interrupt Enable Register bit definitions.
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* These bits are associated with the XTG_MSTERR_INTR_OFFSET register.
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* @{
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*/
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#define XTG_MSTERR_INTR_MINTREN_MASK 0x00008000 /**< Master Err
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Interrupt Enable */
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/*@}*/
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/** @name Config Status Register bit definitions.
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* These bits are associated with the XTG_CFG_STS_OFFSET register.
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* @{
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*/
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#define XTG_CFG_STS_MWIDTH_SHIFT 28 /**< Master Width Shift */
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#define XTG_CFG_STS_MWIDTH_MASK 0x70000000 /**< Master Width Mask */
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#define XTG_CFG_STS_SWIDTH_SHIFT 25 /**< Slave Width Shift */
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#define XTG_CFG_STS_SWIDTH_MASK 0x0E000000 /**< Slave Width Mask */
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#define XTG_CFG_STS_MFULL_MASK 0x01000000 /**< Full Mode */
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#define XTG_CFG_STS_MBASIC_MASK 0x00800000 /**< Basic Mode */
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/*@}*/
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/*@}*/
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/** @name Streaming Control Register bit definitions.
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* These bits are associated with the XTG_STR_CFG_OFFSET register.
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* @{
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*/
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#define XTG_STREAM_CNTL_VER_SHIFT 24 /**< Version Shift */
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#define XTG_STREAM_CNTL_VER_MASK 0xFF000000 /**< Version Mask */
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#define XTG_STREAM_CNTL_TD_SHIFT 1 /**< Transfer Done Shift */
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#define XTG_STREAM_CNTL_TD_MASK 0x00000002 /**< Transfer Done Mask */
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#define XTG_STREAM_CNTL_STEN_MASK 0x00000001 /**< Streaming Enable Mask */
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#define XTG_STREAM_CNTL_RESET_MASK 0x00000000 /**< Streaming Disable Mask */
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/*@}*/
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/*@}*/
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/** @name Streaming Config Register bit definitions.
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* These bits are associated with the XTG_STR_CFG_OFFSET register.
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* @{
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*/
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#define XTG_STREAM_CFG_PDLY_SHIFT 16 /**< Programmable Delay Shift */
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#define XTG_STREAM_CFG_PDLY_MASK 0xFFFF0000 /**< Programmable Delay Mask */
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#define XTG_STREAM_CFG_TDEST_SHIFT 8 /**< TDEST PORT Shift */
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#define XTG_STREAM_CFG_TDEST_MASK 0x0000FF00 /**< TDEST PORT Mask */
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#define XTG_STREAM_CFG_RANDLY_SHIFT 1 /**< Random Delay Shift */
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#define XTG_STREAM_CFG_RANDLY_MASK 0x00000002 /**< Random Delay Mask */
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#define XTG_STREAM_CFG_RANDL_MASK 0x00000001 /**< Random Length Mask */
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/*@}*/
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/*@}*/
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/** @name Streaming Transfer Length Register bit definitions.
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* These bits are associated with the XTG_STR_TL_OFFSET register.
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* @{
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*/
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#define XTG_STREAM_TL_TCNT_SHIFT 16 /**< Transfer Count Shift */
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#define XTG_STREAM_TL_TCNT_MASK 0xFFFF0000 /**< Transfer Count Mask */
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#define XTG_STREAM_TL_TLEN_MASK 0x0000FFFF /**< Transfer Length Mask */
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/*@}*/
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/*@}*/
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/** @name Static Control Register bit definitions.
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* These bits are associated with the XTG_STATIC_CNTL_OFFSET register.
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* @{
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*/
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#define XTG_STATIC_CNTL_VER_SHIFT 24 /**< Version Shift */
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#define XTG_STATIC_CNTL_VER_MASK 0xFF000000 /**< Version Mask */
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#define XTG_STATIC_CNTL_TD_SHIFT 1 /**< Transfer Done Shift */
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#define XTG_STATIC_CNTL_TD_MASK 0x00000002 /**< Transfer Done Mask */
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#define XTG_STATIC_CNTL_STEN_MASK 0x00000001 /**< Static enable Mask */
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#define XTG_STATIC_CNTL_RESET_MASK 0x00000000 /**< Static Disable Mask */
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/*@}*/
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/*@}*/
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/** @name Static Length Register bit definitions.
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* These bits are associated with the XTG_STATIC_LEN_OFFSET register.
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* @{
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*/
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#define XTG_STATIC_LEN_BLEN_MASK 0x000000FF /**< Burst length Mask */
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/*@}*/
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/** @name Axi Traffic Generator Command Entry field mask/shifts
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* @{
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*/
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#define XTG_ADDR_MASK 0xFFFFFFFF /**< Driven to a*_addr line */
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#define XTG_LEN_MASK 0xFF /**< Driven to a*_len line */
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#define XTG_LOCK_MASK 0x1 /**< Driven to a*_lock line */
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#define XTG_BURST_MASK 0x3 /**< Driven to a*_burst line */
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#define XTG_SIZE_MASK 0x7 /**< Driven to a*_size line */
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#define XTG_ID_MASK 0x3F /**< Driven to a*_id line */
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#define XTG_PROT_MASK 0x7 /**< Driven to a*_prot line */
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#define XTG_LAST_ADDR_MASK 0x7 /**< Last address */
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#define XTG_VALID_CMD_MASK 0x1 /**< Valid Command */
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#define XTG_MSTRAM_INDEX_MASK 0x1FFF /**< Master RAM Index */
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#define XTG_OTHER_DEPEND_MASK 0x1FF /**< Other depend Command no */
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#define XTG_MY_DEPEND_MASK 0x1FF /**< My depend command no */
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#define XTG_QOS_MASK 0xF /**< Driven to a*_qos line */
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#define XTG_USER_MASK 0xFF /**< Driven to a*_user line */
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#define XTG_CACHE_MASK 0xF /**< Driven to a*_cache line */
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#define XTG_EXPECTED_RESP_MASK 0x7 /**< Expected response */
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#define XTG_ADDR_SHIFT 0 /**< Driven to a*_addr line */
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#define XTG_LEN_SHIFT 0 /**< Driven to a*_len line */
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#define XTG_LOCK_SHIFT 8 /**< Driven to a*_lock line */
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#define XTG_BURST_SHIFT 10 /**< Driven to a*_burst line */
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#define XTG_SIZE_SHIFT 12 /**< Driven to a*_size line */
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#define XTG_ID_SHIFT 15 /**< Driven to a*_id line */
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#define XTG_PROT_SHIFT 21 /**< Driven to a*_prot line */
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#define XTG_LAST_ADDR_SHIFT 28 /**< Last address */
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#define XTG_VALID_CMD_SHIFT 31 /**< Valid Command */
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#define XTG_MSTRAM_INDEX_SHIFT 0 /**< Master RAM Index */
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#define XTG_OTHER_DEPEND_SHIFT 13 /**< Other depend cmd num */
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#define XTG_MY_DEPEND_SHIFT 22 /**< My depend cmd num */
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#define XTG_QOS_SHIFT 16 /**< Driven to a*_qos line */
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#define XTG_USER_SHIFT 8 /**< Driven to a*_user line */
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#define XTG_CACHE_SHIFT 4 /**< Driven to a*_cache line */
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#define XTG_EXPECTED_RESP_SHIFT 0 /**< Expected response */
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/*@}*/
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/** @name Axi Traffic Generator Parameter Entry field mask/shifts
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* @{
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*/
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/* Parameter Entry field shift values */
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#define XTG_PARAM_ADDRMODE_SHIFT 24 /**< Address mode */
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#define XTG_PARAM_INTERVALMODE_SHIFT 26 /**< Interval mode */
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#define XTG_PARAM_IDMODE_SHIFT 28 /**< Id mode */
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#define XTG_PARAM_OP_SHIFT 29 /**< Opcode */
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/* PARAM RAM Opcode shift values */
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#define XTG_PARAM_COUNT_SHIFT 0 /**< Repeat/Delay count */
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#define XTG_PARAM_DELAYRANGE_SHIFT 0 /**< Delay Range */
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#define XTG_PARAM_DELAY_SHIFT 8 /**< FIXED RPT Delay count */
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#define XTG_PARAM_ADDRRANGE_SHIFT 20 /**< Address Range */
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/* Parameter Entry field mask values */
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#define XTG_PARAM_ADDRMODE_MASK 0x3 /**< Address mode */
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#define XTG_PARAM_INTERVALMODE_MASK 0x3 /**< Interval mode */
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#define XTG_PARAM_IDMODE_MASK 0x1 /**< Id mode */
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#define XTG_PARAM_OP_MASK 0x7 /**< Opcode */
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/* PARAM RAM Opcode mask values */
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#define XTG_PARAM_COUNT_MASK 0xFFFFFF/**< Repeat/Delay count */
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#define XTG_PARAM_DELAYRANGE_MASK 0xFF /**< Delay Range */
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#define XTG_PARAM_DELAY_MASK 0xFFF /**< FIXED RPT Delay count */
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#define XTG_PARAM_ADDRRANGE_MASK 0xF /**< Address Range */
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/* PARAM RAM Opcode values */
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#define XTG_PARAM_OP_NOP 0 /**< NOP mode */
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#define XTG_PARAM_OP_RPT 1 /**< Repeat mode */
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#define XTG_PARAM_OP_DELAY 2 /**< Delay mode */
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#define XTG_PARAM_OP_FIXEDRPT 3 /**< Fixed Repeat Delay */
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/* PARAM RAM Address mode values */
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#define XTG_PARAM_OP_ADDRMODE_CONST 0 /**< Constant Addr mode */
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#define XTG_PARAM_OP_ADDRMODE_INCR 1 /**< Increment Addr mode */
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#define XTG_PARAM_OP_ADDRMODE_RAND 2 /**< Random Addr mode */
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/* PARAM RAM Interval mode values */
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#define XTG_PARAMOP_INTERVALMODE_CONST 0 /**< Constant Interval mode */
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#define XTG_PARAMOP_INTERVALMODE_RAND 1 /**< Random Interval mode */
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/*@}*/
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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/**
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*
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* XTrafGen_ReadReg returns the value read from the register specified by
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* <i>RegOffset</i>.
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*
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* @param BaseAddress is the base address of the Axi TrafGen device.
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* @param RegOffset is the offset of the register to be read.
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*
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* @return Returns the 32-bit value of the register.
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*
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* @note C-style signature:
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* u32 XTrafGen_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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*****************************************************************************/
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#define XTrafGen_ReadReg(BaseAddress, RegOffset) \
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(Xil_In32(((BaseAddress) + (RegOffset))))
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/****************************************************************************/
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/**
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*
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* XTrafGen_WriteReg, writes <i>Data</i> to the register specified by
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* <i>RegOffset</i>.
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*
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* @param BaseAddress is the base address of the Axi TrafGen device.
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* @param RegOffset is the offset of the register to be written.
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* @param Data is the 32-bit value to write to the register.
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void XTrafGen_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
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*
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*****************************************************************************/
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#define XTrafGen_WriteReg(BaseAddress, RegOffset, Data) \
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Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
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/****************************************************************************/
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/**
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*
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* XTrafGen_ReadParamRam returns the value read from the Parameter RAM
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* specified by <i>Offset</i>.
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*
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* @param BaseAddress is the base address of the Axi TrafGen device.
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* @param Offset is the offset of the Parameter RAM to be read.
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*
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* @return Returns the 32-bit value of the memory location.
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*
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* @note C-style signature:
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* u32 XTrafGen_ReadParamRam(u32 BaseAddress, u32 Offset)
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*
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*****************************************************************************/
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#define XTrafGen_ReadParamRam(BaseAddress, Offset) \
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(Xil_In32(((BaseAddress) + XTG_PARAM_RAM_OFFSET + (Offset))))
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/****************************************************************************/
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/**
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*
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* XTrafGen_WriteParamRam, writes <i>Data</i> to the Parameter RAM
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* specified by <i>Offset</i>.
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*
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* @param BaseAddress is the base address of the Axi TrafGen device.
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* @param Offset is the offset of the location in Parameter RAM
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* to be written.
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* @param Data is the 32-bit value to write to the Parameter RAM.
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void XTrafGen_WriteParamRam(u32 BaseAddress, u32 Offset, u32 Data)
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*
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*****************************************************************************/
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#define XTrafGen_WriteParamRam(BaseAddress, Offset, Data) \
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Xil_Out32(((BaseAddress) + XTG_PARAM_RAM_OFFSET + (Offset)), (Data))
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/****************************************************************************/
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/**
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*
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* XTrafGen_ReadCmdRam returns the value read from the Command RAM
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* specified by <i>Offset</i>.
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*
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* @param BaseAddress is the base address of the Axi TrafGen device.
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* @param Offset is the offset of the Command RAM to be read.
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*
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* @return Returns the 32-bit value of the memory location.
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*
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* @note C-style signature:
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* u32 XTrafGen_ReadCmdRam(u32 BaseAddress, u32 Offset)
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*
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*****************************************************************************/
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#define XTrafGen_ReadCmdRam(BaseAddress, Offset) \
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(Xil_In32(((BaseAddress) + XTG_COMMAND_RAM_OFFSET + (Offset))))
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/****************************************************************************/
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/**
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|
*
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|
* XTrafGen_WriteCmdRam, writes <i>Data</i> to the Command RAM specified by
|
|
* <i>Offset</i>.
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|
*
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|
* @param BaseAddress is the base address of the Axi TrafGen device.
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* @param Offset is the offset of the location in Command RAM
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|
* to be written.
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|
* @param Data is the 32-bit value to write to the Command RAM.
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|
*
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|
* @return None.
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|
*
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|
* @note
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|
* C-style signature:
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|
* void XTrafGen_WriteCmdRam(u32 BaseAddress, u32 Offset, u32 Data)
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|
*
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|
*****************************************************************************/
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|
#define XTrafGen_WriteCmdRam(BaseAddress, Offset, Data) \
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|
Xil_Out32(((BaseAddress) + XTG_COMMAND_RAM_OFFSET + (Offset)), (Data))
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|
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|
/****************************************************************************/
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|
/**
|
|
*
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|
* XTrafGen_ReadMasterRam returns the value read from the Master RAM
|
|
* specified by <i>Offset</i>.
|
|
*
|
|
* @param BaseAddress is the base address of the Axi TrafGen device.
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|
* @param Offset is the offset of the Master RAM to be read.
|
|
*
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|
* @return Returns the 32-bit value of the memory location.
|
|
*
|
|
* @note C-style signature:
|
|
* u32 XTrafGen_ReadMasterRam(u32 BaseAddress, u32 Offset)
|
|
*
|
|
*****************************************************************************/
|
|
#define XTrafGen_ReadMasterRam(BaseAddress, Offset) \
|
|
(Xil_In32(((BaseAddress) + XTG_MASTER_RAM_OFFSET + (Offset))))
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
*
|
|
* XTrafGen_WriteMasterRam, writes <i>Data</i> to the Master RAM specified
|
|
* by <i>Offset</i>.
|
|
*
|
|
* @param BaseAddress is the base address of the Axi TrafGen device.
|
|
* @param Offset is the offset of the location in Master RAM
|
|
* to be written.
|
|
* @param Data is the 32-bit value to write to the Master RAM.
|
|
*
|
|
* @return None.
|
|
*
|
|
* @note
|
|
* C-style signature:
|
|
* void XTrafGen_WriteMasterRam(u32 BaseAddress, u32 Offset, u32 Data)
|
|
*
|
|
*****************************************************************************/
|
|
#define XTrafGen_WriteMasterRam(BaseAddress, Offset, Data) \
|
|
Xil_Out32(((BaseAddress) + XTG_MASTER_RAM_OFFSET + (Offset)), (Data))
|
|
|
|
#ifdef __cplusplus
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|
}
|
|
#endif
|
|
|
|
#endif /* end of protection macro */
|