152 lines
3.6 KiB
C
152 lines
3.6 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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#include "xparameters.h"
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#include "xipipsu.h"
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/*
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* The configuration table for devices
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*/
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XIpiPsu_Config XIpiPsu_ConfigTable[] =
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{
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{
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XPAR_PSU_IPI_0_DEVICE_ID,
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XPAR_PSU_IPI_0_BASE_ADDRESS,
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XPAR_PSU_IPI_0_BIT_MASK,
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XPAR_PSU_IPI_0_BUFFER_INDEX,
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XPAR_PSU_IPI_0_INT_ID,
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XPAR_XIPIPSU_NUM_TARGETS,
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{
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{
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XPAR_PSU_IPI_0_BIT_MASK,
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XPAR_PSU_IPI_0_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_1_BIT_MASK,
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XPAR_PSU_IPI_1_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_2_BIT_MASK,
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XPAR_PSU_IPI_2_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_3_BIT_MASK,
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XPAR_PSU_IPI_3_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_4_BIT_MASK,
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XPAR_PSU_IPI_4_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_5_BIT_MASK,
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XPAR_PSU_IPI_5_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_6_BIT_MASK,
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XPAR_PSU_IPI_6_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_7_BIT_MASK,
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XPAR_PSU_IPI_7_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_8_BIT_MASK,
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XPAR_PSU_IPI_8_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_9_BIT_MASK,
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XPAR_PSU_IPI_9_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_10_BIT_MASK,
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XPAR_PSU_IPI_10_BUFFER_INDEX
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}
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}
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},
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{
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XPAR_PSU_IPI_7_DEVICE_ID,
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XPAR_PSU_IPI_7_BASE_ADDRESS,
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XPAR_PSU_IPI_7_BIT_MASK,
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XPAR_PSU_IPI_7_BUFFER_INDEX,
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XPAR_PSU_IPI_7_INT_ID,
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XPAR_XIPIPSU_NUM_TARGETS,
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{
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{
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XPAR_PSU_IPI_0_BIT_MASK,
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XPAR_PSU_IPI_0_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_1_BIT_MASK,
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XPAR_PSU_IPI_1_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_2_BIT_MASK,
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XPAR_PSU_IPI_2_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_3_BIT_MASK,
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XPAR_PSU_IPI_3_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_4_BIT_MASK,
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XPAR_PSU_IPI_4_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_5_BIT_MASK,
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XPAR_PSU_IPI_5_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_6_BIT_MASK,
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XPAR_PSU_IPI_6_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_7_BIT_MASK,
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XPAR_PSU_IPI_7_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_8_BIT_MASK,
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XPAR_PSU_IPI_8_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_9_BIT_MASK,
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XPAR_PSU_IPI_9_BUFFER_INDEX
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},
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{
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XPAR_PSU_IPI_10_BIT_MASK,
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XPAR_PSU_IPI_10_BUFFER_INDEX
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}
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}
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}
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};
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