5125df28f8
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
415 lines
15 KiB
C
415 lines
15 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xhdcp1x_hw.h
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* @addtogroup hdcp1x_v1_0
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* @{
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*
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* This header file contains identifiers and register-level core functions (or
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* macros) that can be used to access the Xilinx HDCP cipher core.
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*
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* For more information about the operation of this core see the hardware
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* specification and documentation in the higher level driver xhdcp1x_ciper.h
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* file.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------------------
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* 1.00 fidus 07/16/15 Initial release.
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* </pre>
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*
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******************************************************************************/
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#ifndef XHDCP1X_HW_H
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/**< Prevent circular inclusions by using protection macros */
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#define XHDCP1X_HW_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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// HDCP Cipher register offsets
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#define XHDCP1X_CIPHER_REG_VERSION (0x0000u) /**< Version register
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offset */
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#define XHDCP1X_CIPHER_REG_TYPE (0x0004u) /**< Type register offset */
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#define XHDCP1X_CIPHER_REG_SCRATCH (0x0008u) /**< Scratch pad register
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offset */
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#define XHDCP1X_CIPHER_REG_CONTROL (0x000Cu) /**< Control register
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offset */
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#define XHDCP1X_CIPHER_REG_STATUS (0x0010u) /**< Status register
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offset */
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#define XHDCP1X_CIPHER_REG_INTERRUPT_MASK (0x0014u) /**< Interrupt Mask
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register offset */
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#define XHDCP1X_CIPHER_REG_INTERRUPT_STATUS \
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(0x0018u) /**< Interrupt Status
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register offset */
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#define XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H \
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(0x0020u) /**< Encryption Enable (High)
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register offset */
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#define XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L \
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(0x0024u) /**< Encryption Enable (Low)
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register offset */
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#define XHDCP1X_CIPHER_REG_KEYMGMT_CONTROL \
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(0x002Cu) /**< Key Management Control
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register offset */
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#define XHDCP1X_CIPHER_REG_KEYMGMT_STATUS (0x0030u) /**< Key Management Status
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register offset */
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#define XHDCP1X_CIPHER_REG_KSV_LOCAL_H (0x0038u) /**< Local KSV (High)
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register offset */
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#define XHDCP1X_CIPHER_REG_KSV_LOCAL_L (0x003Cu) /**< Local KSV (Low) register
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offset */
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#define XHDCP1X_CIPHER_REG_KSV_REMOTE_H (0x0040u) /**< Remote KSV (High)
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offset */
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#define XHDCP1X_CIPHER_REG_KSV_REMOTE_L (0x0044u) /**< Remote KSV (Low)
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register offset */
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#define XHDCP1X_CIPHER_REG_Km_H (0x0048u) /**< Km (High) register
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offset */
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#define XHDCP1X_CIPHER_REG_Km_L (0x004Cu) /**< Km (Low) register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_CONTROL \
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(0x0050u) /**< Cipher Control register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_STATUS (0x0054u) /**< Cipher Status register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Bx (0x0058u) /**< Cipher Bx register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_By (0x005Cu) /**< Cipher By register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Bz (0x0060u) /**< Cipher Bz register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Kx (0x0064u) /**< Cipher Kx register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Ky (0x0068u) /**< Cipher Ky register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Kz (0x006Cu) /**< Cipher Kz register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Mi_H (0x0070u) /**< Cipher Mi (High)
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register offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Mi_L (0x0074u) /**< Cipher Mi (Low) register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Ri (0x0078u) /**< Cipher Ri register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Ro (0x007Cu) /**< Cipher Ro register
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offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Mo_H (0x0080u) /**< Cipher Mo (High)
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register offset */
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#define XHDCP1X_CIPHER_REG_CIPHER_Mo_L (0x0084u) /**< Cipher Mo (Low) register
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offset */
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// HDCP Cipher register bit mask definitions
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#define XHDCP1X_CIPHER_BITMASK_TYPE_PROTOCOL \
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(0x03u << 0) /**< Protocol bitmask in
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Type register */
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#define XHDCP1X_CIPHER_BITMASK_TYPE_DIRECTION \
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(0x01u << 2) /**< Direction bitmask in
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Type register */
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#define XHDCP1X_CIPHER_BITMASK_CONTROL_ENABLE \
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(0x01u << 0) /**< Enable bitmask in
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Control register */
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#define XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE \
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(0x01u << 1) /**< Update bitmask in
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Control register */
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#define XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES \
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(0x07u << 4) /**< Num Lanes bitmask in
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Control register */
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#define XHDCP1X_CIPHER_BITMASK_CONTROL_RESET \
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(0x01u << 31) /**< Reset bitmask in
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Control register */
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#define XHDCP1X_CIPHER_BITMASK_INTERRUPT_LINK_FAIL \
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(0x01u << 0) /**< Link Failure bitmask
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in Interrupt register(s) */
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#define XHDCP1X_CIPHER_BITMASK_INTERRUPT_Ri_UPDATE \
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(0x01u << 1) /**< Ri bitmask in
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Interrupt register(s) */
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#define XHDCP1X_CIPHER_BITMASK_KEYMGMT_CONTROL_LOCAL_KSV \
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(0x01u << 0) /**< Read Local KSV
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bitmask in Key Management
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Control register */
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#define XHDCP1X_CIPHER_BITMASK_KEYMGMT_CONTROL_BEGIN_Km \
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(0x01u << 1) /**< Being Km bitmask in
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Key Management Control
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register */
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#define XHDCP1X_CIPHER_BITMASK_KEYMGMT_CONTROL_ABORT_Km \
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(0x01u << 2) /**< Abort Km bitmask in
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Key Management Control
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register */
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#define XHDCP1X_CIPHER_BITMASK_KEYMGMT_CONTROL_SET_SELECT \
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(0x07u << 16) /**< Key Set Select
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bitmask in Key Management
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Control register */
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#define XHDCP1X_CIPHER_BITMASK_KEYMGMT_STATUS_KSV_READY \
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(0x01u << 0) /**< Local KSV ready
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bitmask in Key Management Status
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register */
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#define XHDCP1X_CIPHER_BITMASK_KEYMGMT_STATUS_Km_READY \
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(0x01u << 1) /**< Km Value ready
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bitmask in Key Management Status
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register */
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#define XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_XOR_ENABLE \
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(0x01u << 0) /**< XOR Enable bitmask
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in Cipher Control register */
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#define XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_REQUEST \
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(0x07u << 8) /**< Request bitmask in
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Cipher Control register */
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#define XHDCP1X_CIPHER_BITMASK_CIPHER_STATUS_XOR_IN_PROG \
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(0x01u << 0) /**< XOR In Progress
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bitmask in Cipher Status
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register */
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#define XHDCP1X_CIPHER_BITMASK_CIPHER_STATUS_REQUEST_IN_PROG \
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(0x07u << 8) /**< Request In Progress
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bitmask in Cipher Status
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register */
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// HDCP Cipher register bit value definitions
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#define XHDCP1X_CIPHER_VALUE_TYPE_PROTOCOL_DP \
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(0x00u << 0) /**< DP Protocol value in
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Type register */
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#define XHDCP1X_CIPHER_VALUE_TYPE_PROTOCOL_HDMI \
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(0x01u << 0) /**< HDMI Protocol value
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in Type register */
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#define XHDCP1X_CIPHER_VALUE_TYPE_DIRECTION_RX \
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(0x00u << 2) /**< RX Direction value
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in Type register */
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#define XHDCP1X_CIPHER_VALUE_TYPE_DIRECTION_TX \
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(0x01u << 2) /**< TX Direction value
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in Type register */
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#define XHDCP1X_CIPHER_VALUE_CIPHER_CONTROL_REQUEST_BLOCK \
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(0x01u << 8) /**< Block Request value
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in Cipher Control register */
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#define XHDCP1X_CIPHER_VALUE_CIPHER_CONTROL_REQUEST_REKEY \
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(0x01u << 9) /**< ReKey Request value
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in Cipher Control register */
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#define XHDCP1X_CIPHER_VALUE_CIPHER_CONTROL_REQUEST_RNG \
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(0x01u << 10) /**< RNG Request value in
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Cipher Control register */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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// Register access macro definition
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#define XHdcp1x_In32 Xil_In32 /**< Input Operations */
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#define XHdcp1x_Out32 Xil_Out32 /**< Output Operations */
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/*****************************************************************************/
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/**
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*
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* This macro reads a value from a HDCP cipher register. A 32 bit read is
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* always performed.
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*
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* @param BaseAddress is the base address of the HDCP cipher core instance.
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* @param RegOffset is the register offset of the register
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*
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* @return
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* The 32-bit value of the register.
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*
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* @note
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* C-style: u32 XHdcp1x_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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******************************************************************************/
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#define XHdcp1x_ReadReg(BaseAddress, RegOffset) \
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XHdcp1x_In32((BaseAddress) + ((u32)RegOffset))
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/*****************************************************************************/
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/**
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*
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* This macro writes a value to a HDCP cipher register. A 32 bit write is
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* always performed.
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*
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* @param BaseAddress is the base address of the HDCP cipher core instance.
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* @param RegOffset is the register offset of the register
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* @param Data is the 32-bit value to write into the register.
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*
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* @return
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* None.
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*
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* @note
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* C-style: void XHdcp1x_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
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*
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******************************************************************************/
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#define XHdcp1x_WriteReg(BaseAddress, RegOffset, Data) \
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XHdcp1x_Out32((BaseAddress) + ((u32)RegOffset), (u32)(Data))
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/*****************************************************************************/
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/**
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* This queries a cipher to determine if it is enabled.
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*
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* @param InstancePtr is the instance to query.
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*
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* @return Truth value indicating transmitter (TRUE) or not (FALSE).
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*
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* @note None.
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*
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******************************************************************************/
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#define XHdcp1x_CipherIsEnabled(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_CONTROL) & \
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XHDCP1X_CIPHER_BITMASK_CONTROL_ENABLE) != 0)
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/*****************************************************************************/
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/**
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* This queries a cipher to determine if the XOR (encryption) function is
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* currently in progress.
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*
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* @param InstancePtr is the instance to query.
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*
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* @return Truth value indicating in progress (TRUE) or not (FALSE).
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*
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* @note None.
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*
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******************************************************************************/
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#define XHdcp1x_CipherXorInProgress(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_CIPHER_STATUS) & \
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XHDCP1X_CIPHER_BITMASK_CIPHER_STATUS_XOR_IN_PROG) != 0)
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/*****************************************************************************/
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/**
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* This queries a cipher to determine if the local KSV is ready to read.
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*
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* @param InstancePtr is the instance to query.
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*
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* @return Truth value indicating ready (TRUE) or not (FALSE).
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*
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* @note None.
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*
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******************************************************************************/
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#define XHdcp1x_CipherLocalKsvReady(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_KEYMGMT_STATUS) & \
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XHDCP1X_CIPHER_BITMASK_KEYMGMT_STATUS_KSV_READY) != 0)
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/*****************************************************************************/
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/**
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* This queries a cipher to determine if the Km value is ready.
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*
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* @param InstancePtr is the instance to query.
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*
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* @return Truth value indicating ready (TRUE) or not (FALSE).
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*
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* @note None.
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*
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******************************************************************************/
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#define XHdcp1x_CipherKmReady(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_KEYMGMT_STATUS) & \
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XHDCP1X_CIPHER_BITMASK_KEYMGMT_STATUS_Km_READY) != 0)
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/*****************************************************************************/
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/**
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*
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* This macro checks if a core supports the Display Port protocol
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*
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* @param InstancePtr is a pointer to the XHdcp1x core instance.
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*
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* @return Truth value indicating DP (TRUE) or not (FALSE)
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*
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******************************************************************************/
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#define XHdcp1x_IsDP(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_TYPE) & XHDCP1X_CIPHER_BITMASK_TYPE_PROTOCOL) \
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== XHDCP1X_CIPHER_VALUE_TYPE_PROTOCOL_DP)
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/*****************************************************************************/
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/**
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*
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* This macro checks if a core supports the HDMI protocol
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*
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* @param InstancePtr is a pointer to the XHdcp1x core instance.
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*
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* @return Truth value indicating HDMI (TRUE) or not (FALSE)
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*
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******************************************************************************/
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#define XHdcp1x_IsHDMI(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_TYPE) & XHDCP1X_CIPHER_BITMASK_TYPE_PROTOCOL) \
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== XHDCP1X_CIPHER_VALUE_TYPE_PROTOCOL_HDMI)
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/*****************************************************************************/
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/**
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*
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* This macro checks if a core supports the receive direction
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*
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* @param InstancePtr is a pointer to the XHdcp1x core instance.
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*
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* @return Truth value indicating receive (TRUE) or not (FALSE)
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*
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******************************************************************************/
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#define XHdcp1x_IsRX(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_TYPE) & XHDCP1X_CIPHER_BITMASK_TYPE_DIRECTION) \
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== XHDCP1X_CIPHER_VALUE_TYPE_DIRECTION_RX)
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/*****************************************************************************/
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/**
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*
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* This macro checks if a core supports the transmit direction
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*
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* @param InstancePtr is a pointer to the XHdcp1x core instance.
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*
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* @return Truth value indicating transmit (TRUE) or not (FALSE)
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*
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******************************************************************************/
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#define XHdcp1x_IsTX(InstancePtr) \
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((XHdcp1x_ReadReg((InstancePtr)->Config.BaseAddress, \
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XHDCP1X_CIPHER_REG_TYPE) & XHDCP1X_CIPHER_BITMASK_TYPE_DIRECTION) \
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== XHDCP1X_CIPHER_VALUE_TYPE_DIRECTION_TX)
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/************************** Function Prototypes ******************************/
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/************************** Variable Declarations ****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif /* XHDCP1X_HW_H */
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/** @} */
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