6a08b60322
This patch updates the doxygen for the drivers wdtps,wdttb,xadcps,usb,usbps to include .h files in the listof files provided in the index.html file. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
58 lines
2.9 KiB
HTML
Executable file
58 lines
2.9 KiB
HTML
Executable file
<html>
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<head>
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<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
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<title>
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Xilinx Driver wdtps v2_0: wdtps v2_0
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</title>
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<link href="doxygen_kalyanidocs/doc/css/driver_api_doxygen.css" rel="stylesheet" type="text/css">
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</head>
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<h3 class="PageHeader">Xilinx Processor IP Library</h3>
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<hl>Software Drivers</hl>
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<hr class="whs1">
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<!-- Generated by Doxygen 1.6.1 -->
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<div class="navigation" id="top">
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<div class="tabs">
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<ul>
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<li class="current"><a href="index.html"><span>Main Page</span></a></li>
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<li><a href="annotated.html"><span>Classes</span></a></li>
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<li><a href="files.html"><span>Files</span></a></li>
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</ul>
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</div>
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</div>
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<div class="contents">
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<h1>wdtps v2_0</h1><p>The Xilinx watchdog timer driver supports the Xilinx watchdog timer hardware.</p>
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<p>The Xilinx watchdog timer (WDT) driver supports the following features:</p>
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<ul>
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<li>Both Interrupt driven and Polled mode</li>
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<li>enabling and disabling the watchdog timer</li>
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<li>restarting the watchdog.</li>
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<li>initializing the most significant digit of the counter restart value.</li>
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<li>multiple individually enabling/disabling outputs</li>
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</ul>
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<p>It is the responsibility of the application to provide an interrupt handler for the watchdog timer and connect it to the interrupt system if interrupt driven mode is desired.</p>
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<p>If interrupt is enabled, the watchdog timer device generates an interrupt when the counter reaches zero.</p>
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<p>If the hardware interrupt signal is not connected/enabled, polled mode is the only option (using IsWdtExpired) for the watchdog.</p>
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<p>The outputs from the WDT are individually enabled/disabled using _EnableOutput()/_DisableOutput(). The clock divisor ratio and initial restart value of the count is configurable using _SetControlValues().</p>
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<p>The reset condition of the hardware has the maximum initial count in the Counter Reset Value (CRV) and the WDT is disabled with the reset enable enabled and the reset length set to 32 clocks. i.e. </p>
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<pre>
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register ZMR = 0x1C2
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register CCR = 0x3FC
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</pre><p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
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<pre>
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MODIFICATION HISTORY:</pre><pre> Ver Who Date Changes
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----- ------ -------- -----------------------------------------------
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1.00a ecm/jz 01/15/10 First release
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1.01a asa 02/15/12 Added tcl file to generate xparameters
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1.02a sg 07/15/12 Removed code/APIs related to External Signal
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Length functionality for CR 658287
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Removed APIs XWdtPs_SetExternalSignalLength,
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XWdtPs_GetExternalSignalLength
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Modified the Self Test to use the Reset Length mask
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for CR 658287
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</pre> </div>
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<p class="Copyright">
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Copyright © 1995-2014 Xilinx, Inc. All rights reserved.
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</p>
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</body>
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</html>
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