2c8f92039d
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
485 lines
20 KiB
C
Executable file
485 lines
20 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xilskey_epshw.h
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*
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*
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* @note None.
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*
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*
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- --------------------------------------------------------
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* 1.00a rpoolla 04/26/13 First release
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*
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*****************************************************************************/
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#ifndef XILSKEY_EPSHW_H
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#define XILSKEY_EPSHW_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "xil_types.h"
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#include "xilskey_utils.h"
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/**
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* Rsa Key hash length in bytes
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*/
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#define XSK_EFUSEPS_RSA_KEY_HASH_LEN_BITS (256)
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#define XSK_EFUSEPS_HAMMING_LOOPS (10)
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#define XSK_EFUSEPS_HAMMING_LENGTH (31)
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#define XSK_EFUSEPS_HAMMING_DATA (26)
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#define XSK_EFUSEPS_SINGLE_MODE (0x0)
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#define XSK_EFUSEPS_REDUNDANCY_MODE (0x1)
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#define XSK_EFUSEPS_READ_MODE_NORMAL (0x1)
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#define XSK_EFUSEPS_READ_MODE_MARGIN_1 (0x2)
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#define XSK_EFUSEPS_READ_MODE_MARGIN_2 (0x3)
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#define XSK_EFUSEPS_ENABLE_PROGRAMMING (0x1)
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#define XSK_EFUSEPS_ENABLE_READ (0x2)
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#define XSK_EFUSEPS_ENABLE_WRITE (0x4)
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#define XSK_EFUSEPS_PRGM_STROBE_WIDTH(RefClk) ((12 * (RefClk))/1000000)
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/**
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* Modified to have max of 32 bit value
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*/
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#define XSK_EFUSEPS_RD_STROBE_WIDTH(RefClk) ((15 * (RefClk))/100000000)
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#define XSK_EFUSEPS_REFCLK_LOW_FREQ (20000000)
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#define XSK_EFUSEPS_REFCLK_HIGH_FREQ (60000000)
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/**
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* PSS eFUSE Register addresses
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*/
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/**
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* eFuse base address
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*/
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#define XSK_EFUSEPS_BASE_ADDRESS (0xF800D000)
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#define XSK_EFUSEPS_WR_LOCK_REG_OFFSET (0x0)
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/**
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* WR_UNLOCK Write 0xDF0D to allow write offset
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*/
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#define XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET (0x4)
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/**
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* WR_LOCKSTA Write protection status offset
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*/
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#define XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET (0x8)
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/**
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* CFG Configuration register offset
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*/
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#define XSK_EFUSEPS_CONFIG_REG_OFFSET (0xC)
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/**
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* STATUS Status register offset
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*/
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#define XSK_EFUSEPS_STATUS_REG_OFFSET (0x10)
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/**
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* CONTROL Control register offset
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*/
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#define XSK_EFUSEPS_CONTROL_REG_OFFSET (0x14)
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/**
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* PGM_STBW eFuse program strobe width register offset
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*/
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#define XSK_EFUSEPS_PGM_STBW_REG_OFFSET (0x18)
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/**
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* RD_STBW eFuse read strobe width register offset
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*/
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#define XSK_EFUSEPS_RD_STBW_REG_OFFSET (0x1C)
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/* WR_LOCK Write 0x767B to disallow write */
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#define XSK_EFUSEPS_WR_LOCK_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_LOCK_REG_OFFSET)
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/**
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* WR_UNLOCK Write 0xDF0D to allow write
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*/
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#define XSK_EFUSEPS_WR_UNLOCK_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET)
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/**
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* WR_LOCKSTA Write protection status
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*/
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#define XSK_EFUSEPS_WR_LOCK_STATUS_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET)
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/**
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* CFG Configuration register
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*/
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#define XSK_EFUSEPS_CONFIG_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_CONFIG_REG_OFFSET)
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/**
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* STATUS Status register
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*/
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#define XSK_EFUSEPS_STATUS_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_STATUS_REG_OFFSET)
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/**
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* CONTROL Control register
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*/
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#define XSK_EFUSEPS_CONTROL_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_CONTROL_REG_OFFSET)
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/**
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* PGM_STBW eFuse program strobe width register
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*/
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#define XSK_EFUSEPS_PGM_STBW_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_PGM_STBW_REG_OFFSET)
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/**
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* RD_STBW eFuse read strobe width register
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*/
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#define XSK_EFUSEPS_RD_STBW_REG (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_RD_STBW_REG_OFFSET)
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/**< PSS eFUSE register bit defines & description */
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/**< XSK_EFUSEPS_WR_LOCK_STATUS_REG (Write Protection Status Register) */
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/** Current state of write protection mode of eFuse subsystem:-
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* 0 Region is writable
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* 1 Region is not writable. Any attempted writes are ignored, but reads will complete as normal.
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*/
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#define XSK_EFUSEPS_WR_LOCK_STATUS_BIT (0x1)
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/**< XSK_EFUSEPS_CONFIG_REG (Configuration Register) */
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/** Redundancy mode, if set, else single mode.
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* This bit only applies to APB access.
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* BISR and eFuse reader always work in redundancy mode.
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*/
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#define XSK_EFUSEPS_CONFIG_REDUNDANCY (0x00010000)
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/** eFuse read/program setup/hold control between address and strobe assert
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* 1 b0 1 ref clock cycle
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* 1 b1 2 ref clock cycles
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*/
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#define XSK_EFUSEPS_CONFIG_TSU_H_A (0x00002000)
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/** eFuse read/program setup/hold control between csb and strobe assert
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* 1 b0 1 ref clock cycle
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* 1 b1 2 ref clock cycles
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*/
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#define XSK_EFUSEPS_CONFIG_TSU_H_CS (0x00001000)
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/**< eFuse program setup/hold control between ps and csb active.*/
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#define XSK_EFUSEPS_CONFIG_TSU_H_PS (0x00000F00)
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/** eFuse read margin control:
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* 00 normal, 01 margin 1, 10 margin 2, 11 - undefined
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*/
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#define XSK_EFUSEPS_CONFIG_MARGIN_RD (0x00000030)
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#define XSK_EFUSEPS_CONFIG_RD_NORMAL (0x00000000)
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#define XSK_EFUSEPS_CONFIG_RD_MARGIN_1 (0x00000010)
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#define XSK_EFUSEPS_CONFIG_RD_MARGIN_2 (0x00000020)
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/** Reference clock scaler
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* 2 b00 bypass clock divider
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* 2 b01 div 2
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* 2 b10 div 4
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* 2 h11 div 8
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*/
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#define XSK_EFUSEPS_CONFIG_CLK_DIV (0x00000003)
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/**< XSK_EFUSEPS_STATUS_REG (Status Register)*/
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/** Status Register containing BISR Controller status, trim value,
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* and security debug info.
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*/
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/**
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* Build in self test finished at boot time
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*/
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#define XSK_EFUSEPS_STATUS_BISR_DONE (0x80000000)
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/**
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* Build in self test finished successfully
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*/
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#define XSK_EFUSEPS_STATUS_BISR_GO (0x40000000)
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/**
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* eFuse box is blank, i.e., not yet been written to, if set
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*/
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#define XSK_EFUSEPS_STATUS_BISR_BLANK (0x00100000)
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/** Security debug status, with authentication
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* 0 security debug enabled
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* 1 security debug disabled
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*/
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#define XSK_EFUSEPS_STATUS_SDEBUG_DIS (0x00010000)
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/** eFuse write protection, if either bit is set,
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* writes to the eFuse box are disabled
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*/
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#define XSK_EFUSEPS_STATUS_WR_PROTECT (0x00003000)
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/**
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* Analog trim value
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*/
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#define XSK_EFUSEPS_STATUS_TRIM (0x000000FC)
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/**
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* XSK_EFUSEPS_CONTROL_REG (Control register for eFuse program,
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* read and write control)
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* eFuse ps control, enable programming if set.
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*/
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#define XSK_EFUSEPS_CONTROL_PS_EN (0x00000010)
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/**
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* eFuse write disable, if set.
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*/
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#define XSK_EFUSEPS_CONTROL_WR_DIS (0x00000002)
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/**
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* eFuse read disable, if set
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*/
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#define XSK_EFUSEPS_CONTROL_RD_DIS (0x00000001)
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#define XSK_EFUSEPS_APB_START_ADDR_OFFSET (0x1000)
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/**
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* eFuse memory APB Customer key second half start address offset
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*/
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#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET (0x20)
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/**
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* eFuse memory APB Customer key second half start address offset
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*/
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#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET (0x24)
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/**
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* eFUSE APB address for ROM 128k CRC enable offset
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*/
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#define XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET (0x28)
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/**
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* eFUSE APB address for RSA authentication enable offset
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*/
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#define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET (0x2C)
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/**
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* eFUSE APB address for RSA uart status enable on MIO48 offset
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*/
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#define XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET (0x5C0)
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/**
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* eFUSE APB address for non-secure INIT_B signaling offset
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*/
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#define XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET (0x5C4)
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/** eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half,
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* and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the
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* Second half(if Single mode is enabled)
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*/
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/**
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* If Redundant mode is enabled only First half addresses are valid.
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* eFuse memory APB Customer key first half start address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET (0x80)
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/**
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* eFuse memory APB Customer key first half end address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET (0x580)
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/**
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* If Single mode is enabled both First and Second half addresses are valid.
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* eFuse memory APB Customer key second half start address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET (0x880)
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/**
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* eFuse memory APB Customer key second half end address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET (0xE00)
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/**
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* Mirror Address = addr + 2nd half start address + mirror offset
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*/
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#define XSK_EFUSEPS_APB_MIRROR_ADDRESS(Addr) (Addr + 0x87C - (2*(Addr%128)))
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/**
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* Following are the Xilinx reserved Tests bits in the First half of the eFUSE block.
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*/
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET (0x80)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41_OFFSET (0x104)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62_OFFSET (0x188)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83_OFFSET (0x20C)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4_OFFSET (0x290)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5_OFFSET (0x314)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6_OFFSET (0x398)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107_OFFSET (0x41C)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128_OFFSET (0x4A0)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149_OFFSET (0x524)
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/**
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* Following are the Xilinx reserved Tests bits in the First half of the eFUSE block.
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*/
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET (0x8FC)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E_OFFSET (0x978)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D_OFFSET (0x9F4)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C_OFFSET (0xA70)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB_OFFSET (0xAEC)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA_OFFSET (0xB68)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9_OFFSET (0xBE4)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318_OFFSET (0xC60)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337_OFFSET (0xCDC)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356_OFFSET (0xD58)
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#define XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_OFFSET (0x1C)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_OFFSET (0x40)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_OFFSET (0x7C)
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#define XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_OFFSET (0x600)
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#define XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_OFFSET (0x7FC)
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/**
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* Following are the Xilinx reserved Tests bits in the Second half of the eFUSE block.
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*/
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#define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET (0x860)
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#define XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF_OFFSET (0x87C)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF_OFFSET (0x800)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF_OFFSET (0x83C)
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#define XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF_OFFSET (0xE00)
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#define XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF_OFFSET (0xFFC)
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/**
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* eFuse memory APB start address
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*/
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#define XSK_EFUSEPS_APB_START_ADDR (XSK_EFUSEPS_BASE_ADDRESS + XSK_EFUSEPS_APB_START_ADDR_OFFSET)
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/*
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* eFuse memory APB Customer key second half start address
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*/
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#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET)
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/*
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* eFuse memory APB Customer key second half start address
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*/
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#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET)
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/*
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* eFUSE APB address for ROM 128k CRC enable
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*/
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#define XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET)
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/*
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* eFUSE APB address for RSA authentication enable
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*/
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#define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET)
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/*
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* eFUSE APB address for RSA uart status enable on MIO48
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*/
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#define XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET)
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/*
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* eFUSE APB address for non-secure INIT_B signaling
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*/
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#define XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET)
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/** eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half,
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* and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the
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* Second half(if Single mode is enabled)
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*/
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/**
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* If Redundant mode is enabled only First half addresses are valid.
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*
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* eFuse memory APB Customer key first half start address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET)
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/**
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* eFuse memory APB Customer key first half end address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET)
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/**
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* If Single mode is enabled both First and Second half addresses are valid.
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*
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* eFuse memory APB Customer key second half start address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET)
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/*
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* eFuse memory APB Customer key second half end address
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*/
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#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET)
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/*
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* Mirror Address = addr + 2nd half start address + mirror offset
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*/
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#define XSK_EFUSEPS_APB_MIRROR_ADDRESS(Addr) (Addr + 0x87C - (2*(Addr%128)))
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/**
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* Following are the Xilinx reserved Tests bits in the First half of the eFUSE block.
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*/
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149_OFFSET)
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/**
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* Following are the Xilinx reserved Tests bits in the First half of the eFUSE block.
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*/
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356 (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356_OFFSET)
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/**
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* Following are the Xilinx reserved Tests bits in the First half of the eFUSE block.
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*/
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#define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR (XSK_EFUSEPS_APB_START_ADDR)
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#define XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_OFFSET)
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#define XSK_EFUSEPS_APB_BISR_BITS_START_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_OFFSET)
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#define XSK_EFUSEPS_APB_BISR_BITS_END_ADDR (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_OFFSET)
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/**
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* Following are the Xilinx reserved Tests bits in the Second half of the eFUSE block.
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*/
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#define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET)
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#define XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF_OFFSET)
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#define XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF_OFFSET)
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#define XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF_OFFSET)
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#define XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF (XSK_EFUSEPS_APB_START_ADDR + XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF_OFFSET)
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/***************** Macros (Inline Functions) Definitions ********************/
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#define XSK_EFUSEPS_CONTROLER_LOCK() Xil_Out32(XSK_EFUSEPS_WR_LOCK_REG,0x767B)
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#define XSK_EFUSEPS_CONTROLER_UNLOCK() Xil_Out32(XSK_EFUSEPS_WR_UNLOCK_REG,0xDF0D)
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#define XSK_EFUSEPS_CONTROLER_LOCK_STATUS() (Xil_In32(XSK_EFUSEPS_WR_LOCK_STATUS_REG) & 0x1)
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#define XSK_EFUSEPS_CONTROLER_OP_MODE() ((Xil_In32(XSK_EFUSEPS_CONFIG_REG) & XSK_EFUSEPS_CONFIG_REDUNDANCY)? 1 : 0)
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/***************************************************************************/
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/**
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* This macro is used to check whether eFuse is write protected or not
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*
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* @return
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* - TRUE if eFuse is write protected.
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* - FALSE is eFuse is not write protected.
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****************************************************************************/
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#define XilSKey_EfusePs_IsEfuseWriteProtected() ((Xil_In32(XSK_EFUSEPS_STATUS_REG) & XSK_EFUSEPS_STATUS_WR_PROTECT)? TRUE : FALSE)
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/************************** Function Prototypes ******************************/
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void XilSKey_EfusePs_GenerateMatrixMap();
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u8 XilSKey_EfusePs_EccDecode(const u8 *Corrupt, u8 *Syndrome);
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void XilSKey_EfusePs_EccEncode(const u8 *InData, u8 *Ecc);
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u32 XilSKey_EfusePs_ControllerConfig(u8 CtrlMode, u32 RefClk, u8 ReadMode);
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u8 XilSKey_EfusePs_IsAddressXilRestricted (u32 Addr);
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void XilSKey_EfusePs_ControllerSetReadWriteEnable(u32 ReadWriteEnable);
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u32 XilSKey_EfusePs_ReadEfuseBit(u32 Addr, u8 *Data);
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u32 XilSKey_EfusePs_WriteEfuseBit(u32 Addr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* End of XILSKEY_EPSHW_H */
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