e2e3bce21e
This patch updates the copy right to 2015. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
367 lines
14 KiB
C
Executable file
367 lines
14 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xaxivdma_hw.h
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*
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* Hardware definition file. It defines the register interface and Buffer
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* Descriptor (BD) definitions.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 07/30/10 First release
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* 2.00a jz 12/10/10 Added support for direct register access mode, v3 core
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* 2.01a jz 01/19/11 Added ability to re-assign BD addresses
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* rkv 03/28/11 Added support for frame store register.
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* 3.00a srt 08/26/11 - Added support for Line Buffer Threshold Registers.
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* - XAXIVDMA_MISMATCH_ERROR flag is added to support Flush
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* on Frame Sync for Mismatch Errors.
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* 4.00a srt 11/21/11 - XAxiVdma_ChannelSetBufferAddr API is changed to
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* support 32 Frame Stores.
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* - XAxiVdma_ChannelConfig API is changed to support
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* modified Park Offset Register bits.
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* - Added APIs:
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* XAxiVdma_FsyncSrcSelect()
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* XAxiVdma_GenLockSourceSelect()
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* XAxiVdma_ChannelHiFrmAddrEnable()
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* XAxiVdma_ChannelHiFrmAddrDisable()
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* 4.01a srt 06/13/12 - Added new error bit mask XAXIVDMA_SR_ERR_SOF_LATE_MASK
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* - XAXIVDMA_MISMATCH_ERROR flag is deprecated.
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* 4.02a srt 10/11/12 - Changed Error bitmasks to support IP version 5.02a.
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* (CR 679959)
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* 4.04a srt 03/03/13 - Support for the GenlockRepeat Control bit (Bit 15)
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* added in the new version of IP v5.04 (CR: 691391)
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* 4.06a srt 04/09/13 - Added support for the newly added S2MM_DMA_IRQ_MASK
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* register (CR 734741)
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* </pre>
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*
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*****************************************************************************/
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#ifndef XAXIVDMA_HW_H_ /* prevent circular inclusions */
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#define XAXIVDMA_HW_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "xil_types.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name Buffer Descriptor Alignment
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* @{
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*/
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#define XAXIVDMA_BD_MINIMUM_ALIGNMENT 0x20 /**< Minimum byte alignment
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requirement for descriptors */
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#define XAXIVDMA_BD_MINIMUM_ALIGNMENT_WD 0x8 /**< Minimum word alignment
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requirement for descriptors */
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/**
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* Maximum number of the frame store
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*/
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#define XAXIVDMA_MAX_FRAMESTORE 32 /**< Maximum # of the frame store */
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/*@}*/
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/** @name Maximum transfer length
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* This is determined by hardware
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* @{
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*/
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#define XAXIVDMA_MAX_VSIZE 0x1FFF /* Max vertical size, 8K */
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#define XAXIVDMA_MAX_HSIZE 0xFFFF /* Max horizontal size, 64K */
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#define XAXIVDMA_MAX_STRIDE 0xFFFF /* Max stride size, 64K */
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#define XAXIVDMA_FRMDLY_MAX 0xF /**< Maximum frame delay */
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/*@}*/
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/**
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* Frame/Line Mismatch Error
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* This is a typical DMA Internal Error, which on detection doesnt require
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* a reset (as opposed to other errors). So a MSB bit is set to identify it,
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* from other DMA Internal Errors.
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*
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*/
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#define XAXIVDMA_MISMATCH_ERROR 0x80000010
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/* | |_ DMA Internal Error Bit.
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* |_______ Set to identify Mismatch Errors.
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*/
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/* Register offset definitions. Register accesses are 32-bit.
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*/
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/** @name Device registers
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* Register sets on TX (Read) and RX (Write) channels are identical
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*
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* The version register is shared by both channels
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* @{
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*/
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#define XAXIVDMA_TX_OFFSET 0x00000000 /**< TX channel registers base */
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#define XAXIVDMA_RX_OFFSET 0x00000030 /**< RX channel registers base */
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#define XAXIVDMA_PARKPTR_OFFSET 0x00000028 /**< Park Pointer Register */
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#define XAXIVDMA_VERSION_OFFSET 0x0000002C /**< Version register */
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/* This set of registers are applicable for both channels. Use
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* XAXIVDMA_TX_OFFSET for the TX channel, and XAXIVDMA_RX_OFFSET for the
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* RX channel
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*/
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#define XAXIVDMA_CR_OFFSET 0x00000000 /**< Channel control */
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#define XAXIVDMA_SR_OFFSET 0x00000004 /**< Status */
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#define XAXIVDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */
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#define XAXIVDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */
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#define XAXIVDMA_HI_FRMBUF_OFFSET 0x00000014 /**< 32 FrameBuf Sel*/
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#define XAXIVDMA_FRMSTORE_OFFSET 0x00000018 /**< Frame Store */
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#define XAXIVDMA_BUFTHRES_OFFSET 0x0000001C /**< Line Buffer Thres */
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#define XAXIVDMA_MM2S_ADDR_OFFSET 0x00000050 /**< MM2S channel Addr */
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#define XAXIVDMA_S2MM_ADDR_OFFSET 0x000000A0 /**< S2MM channel Addr */
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/* This register is specific to S2MM channel
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*/
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#define XAXIVDMA_S2MM_DMA_IRQ_MASK_OFFSET 0x0000003C /**< S2MM Err IRQ Mask*/
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/*@}*/
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/** @name Start Addresses Register Array for a Channel
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*
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* Base offset is set in each channel
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* This set of registers are write only, they can be read when
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* C_ENABLE_VIDPRMTR_READS is 1.
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* @{
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*/
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#define XAXIVDMA_VSIZE_OFFSET 0x00000000 /**< Vertical size */
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#define XAXIVDMA_HSIZE_OFFSET 0x00000004 /**< Horizontal size */
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#define XAXIVDMA_STRD_FRMDLY_OFFSET 0x00000008 /**< Horizontal size */
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#define XAXIVDMA_START_ADDR_OFFSET 0x0000000C /**< Start of address */
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#define XAXIVDMA_START_ADDR_LEN 0x00000004 /**< Each entry is 4 bytes */
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/*@}*/
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/** @name Bitmasks of the XAXIVDMA_CR_OFFSET register
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* @{
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*/
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#define XAXIVDMA_CR_RUNSTOP_MASK 0x00000001 /**< Start/stop DMA channel */
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#define XAXIVDMA_CR_TAIL_EN_MASK 0x00000002 /**< Tail ptr enable or Park */
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#define XAXIVDMA_CR_RESET_MASK 0x00000004 /**< Reset channel */
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#define XAXIVDMA_CR_SYNC_EN_MASK 0x00000008 /**< Gen-lock enable */
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#define XAXIVDMA_CR_FRMCNT_EN_MASK 0x00000010 /**< Frame count enable */
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#define XAXIVDMA_CR_FSYNC_SRC_MASK 0x00000060 /**< Fsync Source Select */
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#define XAXIVDMA_CR_GENLCK_SRC_MASK 0x00000080 /**< Genlock Source Select */
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#define XAXIVDMA_CR_RD_PTR_MASK 0x00000F00 /**< Read pointer number */
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#define XAXIVDMA_CR_GENLCK_RPT_MASK 0x00008000 /**< GenLock Repeat */
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#define XAXIVDMA_CR_RD_PTR_SHIFT 8 /**< Shift for read pointer number */
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/*@}*/
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/** @name Bitmasks of the XAXIVDMA_SR_OFFSET register
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* This register reports status of a DMA channel, including
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* run/stop/idle state, errors, and interrupts
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* @{
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*/
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#define XAXIVDMA_SR_HALTED_MASK 0x00000001 /**< DMA channel halted */
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#define XAXIVDMA_SR_IDLE_MASK 0x00000002 /**< DMA channel idle */
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#define XAXIVDMA_SR_ERR_INTERNAL_MASK 0x00000010 /**< Datamover internal err */
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#define XAXIVDMA_SR_ERR_SLAVE_MASK 0x00000020 /**< Datamover slave err */
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#define XAXIVDMA_SR_ERR_DECODE_MASK 0x00000040 /**< Datamover decode err */
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#define XAXIVDMA_SR_ERR_FSZ_LESS_MASK 0x00000080 /**< FSize Less Mismatch err */
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#define XAXIVDMA_SR_ERR_LSZ_LESS_MASK 0x00000100 /**< LSize Less Mismatch err */
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#define XAXIVDMA_SR_ERR_SG_SLV_MASK 0x00000200 /**< SG slave err */
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#define XAXIVDMA_SR_ERR_SG_DEC_MASK 0x00000400 /**< SG decode err */
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#define XAXIVDMA_SR_ERR_FSZ_MORE_MASK 0x00000800 /**< FSize More Mismatch err */
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#define XAXIVDMA_SR_ERR_ALL_MASK 0x00000FF0 /**< All errors */
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/** @name Bitmask for interrupts
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* These masks are shared by the XAXIVDMA_CR_OFFSET register and
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* the XAXIVDMA_SR_OFFSET register
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* @{
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*/
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#define XAXIVDMA_IXR_FRMCNT_MASK 0x00001000 /**< Frame count intr */
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#define XAXIVDMA_IXR_DELAYCNT_MASK 0x00002000 /**< Delay interrupt */
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#define XAXIVDMA_IXR_ERROR_MASK 0x00004000 /**< Error interrupt */
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#define XAXIVDMA_IXR_COMPLETION_MASK 0x00003000 /**< Completion interrupts */
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#define XAXIVDMA_IXR_ALL_MASK 0x00007000 /**< All interrupts */
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/*@}*/
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/** @name Bitmask and shift for delay and coalesce
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* These masks are shared by the XAXIVDMA_CR_OFFSET register and
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* the XAXIVDMA_SR_OFFSET register
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* @{
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*/
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#define XAXIVDMA_DELAY_MASK 0xFF000000 /**< Delay timeout counter */
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#define XAXIVDMA_FRMCNT_MASK 0x00FF0000 /**< Frame counter */
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#define XAXIVDMA_REGINDEX_MASK 0x00000001 /**< Register Index */
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#define XAXIVDMA_DELAY_SHIFT 24
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#define XAXIVDMA_FRMCNT_SHIFT 16
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/*@}*/
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/** @name Bitmask for the XAXIVDMA_CDESC_OFFSET register
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* @{
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*/
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#define XAXIVDMA_CDESC_CURBD_MASK 0xFFFFFFE0 /**< BD now working on */
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/*@}*/
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/** @name Bitmask for XAXIVDMA_TDESC_OFFSET register
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* @{
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*/
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#define XAXIVDMA_TDESC_CURBD_MASK 0xFFFFFFE0 /**< BD to stop on */
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/*@}*/
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/** @name Bitmask for XAXIVDMA_FRMSTORE_OFFSET register
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* @{
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*/
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#define XAXIVDMA_FRMSTORE_MASK 0x0000003F
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/*@}*/
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/** @name Bitmask for XAXIVDMA_PARKPTR_OFFSET register
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* @{
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*/
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#define XAXIVDMA_PARKPTR_READREF_MASK 0x0000001F /**< Read frame to park on */
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#define XAXIVDMA_PARKPTR_WRTREF_MASK 0x00001F00 /**< Write frame to park on */
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#define XAXIVDMA_PARKPTR_READSTR_MASK 0x001F0000 /**< Current read frame */
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#define XAXIVDMA_PARKPTR_WRTSTR_MASK 0x1F000000 /**< Current write frame */
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#define XAXIVDMA_READREF_SHIFT 0
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#define XAXIVDMA_WRTREF_SHIFT 8
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#define XAXIVDMA_READSTR_SHIFT 16
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#define XAXIVDMA_WRTSTR_SHIFT 24
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#define XAXIVDMA_FRM_MAX 0xF /**< At most 16 frames */
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/*@}*/
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/** @name Bitmask for XAXIVDMA_VERSION_OFFSET register
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* @{
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*/
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#define XAXIVDMA_VERSION_MAJOR_MASK 0xF0000000 /**< Major version */
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#define XAXIVDMA_VERSION_MINOR_MASK 0x0FF00000 /**< Minor version */
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#define XAXIVDMA_VERSION_REV_MASK 0x000F0000 /**< Revision letter */
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#define XAXIVDMA_VERSION_MAJOR_SHIFT 28
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#define XAXIVDMA_VERSION_MINOR_SHIFT 20
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/*@}*/
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/** @name Bitmask for XAXIVDMA_S2MM_IRQ_MASK_OFFSET register
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* @{
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*/
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#define XAXIVDMA_S2MM_IRQ_FSZLESS_SOF_ERLY_MASK 0x00000001 /**< Masks S2MM
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IRQ FSize Less/SOF
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Early Error */
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#define XAXIVDMA_S2MM_IRQ_LSZLESS_EOL_ERLY_MASK 0x00000002 /**< Masks S2MM
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IRQ LSize Less/EOL
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Early Error */
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#define XAXIVDMA_S2MM_IRQ_FSZMORE_SOF_LATE_MASK 0x00000004 /**< Masks S2MM
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IRQ FSize More/SOF
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Late Error */
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#define XAXIVDMA_S2MM_IRQ_LSZMORE_EOL_LATE_MASK 0x00000008 /**< Masks S2MM
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IRQ LSize More/EOL
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Late Error */
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#define XAXIVDMA_S2MM_IRQ_ERR_ALL_MASK 0x0000000F /**< Masks all
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S2MM IRQ Errors */
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/*@}*/
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/** @name Frame Delay shared by start address registers and BDs
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*
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* @{
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*/
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#define XAXIVDMA_VSIZE_MASK 0x00001FFF /**< Vertical size */
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#define XAXIVDMA_HSIZE_MASK 0x0000FFFF /**< Horizontal size */
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#define XAXIVDMA_STRIDE_MASK 0x0000FFFF /**< Stride size */
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#define XAXIVDMA_FRMDLY_MASK 0x0F000000 /**< Frame delay */
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#define XAXIVDMA_FRMDLY_SHIFT 24 /**< Shift for frame delay */
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/*@}*/
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/* Buffer Descriptor (BD) definitions
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*/
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/** @name Buffer Descriptor offsets
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*
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* @{
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*/
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#define XAXIVDMA_BD_NDESC_OFFSET 0x00 /**< Next descriptor pointer */
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#define XAXIVDMA_BD_START_ADDR_OFFSET 0x08 /**< Start address */
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#define XAXIVDMA_BD_VSIZE_OFFSET 0x10 /**< Vertical size */
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#define XAXIVDMA_BD_HSIZE_OFFSET 0x14 /**< Horizontal size */
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#define XAXIVDMA_BD_STRIDE_OFFSET 0x18 /**< Stride size */
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#define XAXIVDMA_BD_NUM_WORDS 7 /**< Total number of words for one BD*/
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#define XAXIVDMA_BD_HW_NUM_BYTES 28 /**< Number of bytes hw used */
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#define XAXIVDMA_BD_BYTES_TO_CLEAR 20 /**< Skip next ptr when clearing */
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/*@}*/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XAxiVdma_In32 Xil_In32
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#define XAxiVdma_Out32 Xil_Out32
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/*****************************************************************************/
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/**
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*
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* Read the given register.
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*
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* @param BaseAddress is the base address of the device
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* @param RegOffset is the register offset to be read
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*
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* @return The 32-bit value of the register
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*
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* @note
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* C-style signature:
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* u32 XAxiVdma_ReadReg(u32 BaseAddress, u32 RegOffset)
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*
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******************************************************************************/
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#define XAxiVdma_ReadReg(BaseAddress, RegOffset) \
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XAxiVdma_In32((BaseAddress) + (RegOffset))
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/*****************************************************************************/
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/**
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*
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* Write the given register.
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*
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* @param BaseAddress is the base address of the device
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* @param RegOffset is the register offset to be written
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* @param Data is the 32-bit value to write to the register
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*
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* @return None.
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*
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* @note
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* C-style signature:
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* void XAxiVdma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
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*
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******************************************************************************/
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#define XAxiVdma_WriteReg(BaseAddress, RegOffset, Data) \
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XAxiVdma_Out32((BaseAddress) + (RegOffset), (Data))
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#ifdef __cplusplus
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}
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#endif
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#endif
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