79 lines
3 KiB
C
79 lines
3 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/**
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*
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* @file xipipsu_hw.h
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* @addtogroup ipipsu_v1_0
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* @{
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*
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* This file contains macro definitions for low level HW related params
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- --- -------- -----------------------------------------------.
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* 1.0 mjr 03/15/15 First release
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XIPIPSU_HW_H_ /* prevent circular inclusions */
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#define XIPIPSU_HW_H_ /* by using protection macros */
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/************************** Constant Definitions *****************************/
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/* Message RAM related params */
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#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
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#define XIPIPSU_MSG_BUF_SIZE 8U /* Size in Words */
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#define XIPIPSU_MAX_BUFF_INDEX 7
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/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
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#define XIPIPSU_BUFFER_OFFSET_GROUP (8U * 2U * 32U)
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#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
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#define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U)
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/* Max Number of IPI slots on the device */
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#define XIPIPSU_MAX_TARGETS 11
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/* Register Offsets for each member of IPI Register Set */
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#define XIPIPSU_TRIG_OFFSET 0x00U
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#define XIPIPSU_OBS_OFFSET 0x04U
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#define XIPIPSU_ISR_OFFSET 0x10U
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#define XIPIPSU_IMR_OFFSET 0x14U
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#define XIPIPSU_IER_OFFSET 0x18U
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#define XIPIPSU_IDR_OFFSET 0x1CU
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/* MASK of all valid IPI bits in above registers */
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#define XIPIPSU_ALL_MASK 0x0F0F0301U
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#endif /* XIPIPSU_HW_H_ */
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/** @} */
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