Xilinx Embedded Software (embeddedsw) Development
d7e056eb66
Bit 21 of DPTX register PHY_CONFIG (0x200) enables 8b10b encoding. In v6.0 of the DPTX core, the default value is '1'. Current driver should keep this value untouched when writing to the PHY_CONFIG register. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> |
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| lib | ||
| XilinxProcessorIPLib/drivers | ||